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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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msm-geni-serial: Use dma_alloc_coherent to avoid dma map/unmap
Use dma_alloc_coherent and dma_free_coherent to avoid dma_map/ dma_unmap calls for every UART rx transfer. Change-Id: Ia2d71d19dc26d96f3c2abe12e22d326d21a2e071 Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
This commit is contained in:
Mukesh Kumar Savaliya
Gerrit - the friendly Code Review server
parent
87279d8c5f
commit
c7ba4adfa9
3 changed files with 84 additions and 46 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -1244,6 +1244,35 @@ int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base,
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}
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EXPORT_SYMBOL(geni_se_tx_dma_prep);
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/**
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* geni_se_rx_dma_start() - Prepare the Serial Engine registers for RX DMA
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transfers.
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* @base: Base address of the SE register block.
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* @rx_len: Length of the RX buffer.
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* @rx_dma: Pointer to store the mapped DMA address.
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*
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* This function is used to prepare the Serial Engine registers for DMA RX.
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*
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* Return: None.
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*/
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void geni_se_rx_dma_start(void __iomem *base, int rx_len, dma_addr_t *rx_dma)
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{
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if (!*rx_dma || !base || !rx_len)
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return;
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geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET);
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geni_write_reg(GENI_SE_DMA_PTR_L(*rx_dma), base, SE_DMA_RX_PTR_L);
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geni_write_reg(GENI_SE_DMA_PTR_H(*rx_dma), base, SE_DMA_RX_PTR_H);
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/* RX does not have EOT bit */
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geni_write_reg(0, base, SE_DMA_RX_ATTR);
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/* Ensure that above register writes went through */
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mb();
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geni_write_reg(rx_len, base, SE_DMA_RX_LEN);
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}
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EXPORT_SYMBOL(geni_se_rx_dma_start);
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/**
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* geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer
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* @wrapper_dev: QUPv3 Wrapper Device to which the RX buffer is mapped.
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@ -1269,12 +1298,8 @@ int geni_se_rx_dma_prep(struct device *wrapper_dev, void __iomem *base,
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if (ret)
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return ret;
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geni_write_reg(7, base, SE_DMA_RX_IRQ_EN_SET);
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geni_write_reg(GENI_SE_DMA_PTR_L(*rx_dma), base, SE_DMA_RX_PTR_L);
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geni_write_reg(GENI_SE_DMA_PTR_H(*rx_dma), base, SE_DMA_RX_PTR_H);
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/* RX does not have EOT bit */
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geni_write_reg(0, base, SE_DMA_RX_ATTR);
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geni_write_reg(rx_len, base, SE_DMA_RX_LEN);
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geni_se_rx_dma_start(base, rx_len, rx_dma);
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return 0;
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}
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EXPORT_SYMBOL(geni_se_rx_dma_prep);
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@ -23,6 +23,7 @@
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#include <linux/tty_flip.h>
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#include <linux/ioctl.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/dma-mapping.h>
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/* UART specific GENI registers */
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#define SE_UART_LOOPBACK_CFG (0x22C)
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@ -1076,7 +1077,6 @@ static void start_rx_sequencer(struct uart_port *uport)
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unsigned int geni_m_irq_en;
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unsigned int geni_status;
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struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
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int ret;
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u32 geni_se_param = UART_PARAM_RFR_OPEN;
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if (port->startup_in_progress)
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@ -1084,17 +1084,11 @@ static void start_rx_sequencer(struct uart_port *uport)
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geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
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if (geni_status & S_GENI_CMD_ACTIVE) {
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if (port->xfer_mode == SE_DMA && !port->rx_dma) {
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if (port->xfer_mode == SE_DMA) {
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IPC_LOG_MSG(port->ipc_log_misc,
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"%s: GENI: 0x%x\n", __func__, geni_status);
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ret = geni_se_rx_dma_prep(port->wrapper_dev,
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uport->membase, port->rx_buf, DMA_RX_BUF_SIZE,
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&port->rx_dma);
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if (ret) {
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IPC_LOG_MSG(port->ipc_log_misc,
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"%s: RX buff Fail %d\n", __func__, ret);
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goto exit_start_rx_sequencer;
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}
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geni_se_rx_dma_start(uport->membase, DMA_RX_BUF_SIZE,
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&port->rx_dma);
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}
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msm_geni_serial_stop_rx(uport);
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}
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@ -1116,21 +1110,14 @@ static void start_rx_sequencer(struct uart_port *uport)
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geni_write_reg_nolog(geni_m_irq_en, uport->membase,
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SE_GENI_M_IRQ_EN);
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} else if (port->xfer_mode == SE_DMA) {
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ret = geni_se_rx_dma_prep(port->wrapper_dev, uport->membase,
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port->rx_buf, DMA_RX_BUF_SIZE, &port->rx_dma);
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if (ret) {
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dev_err(uport->dev, "%s: RX Prep dma failed %d\n",
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__func__, ret);
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msm_geni_serial_stop_rx(uport);
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goto exit_start_rx_sequencer;
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}
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geni_se_rx_dma_start(uport->membase, DMA_RX_BUF_SIZE,
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&port->rx_dma);
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}
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/*
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* Ensure the writes to the secondary sequencer and interrupt enables
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* go through.
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*/
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mb();
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exit_start_rx_sequencer:
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geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
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IPC_LOG_MSG(port->ipc_log_misc, "%s: 0x%x, dma_dbg:0x%x\n", __func__,
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geni_status, geni_read_reg(uport->membase, SE_DMA_DEBUG_REG0));
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@ -1257,12 +1244,9 @@ static void stop_rx_sequencer(struct uart_port *uport)
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msm_geni_serial_abort_rx(uport);
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}
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exit_rx_seq:
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if (port->xfer_mode == SE_DMA && port->rx_dma) {
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if (port->xfer_mode == SE_DMA && port->rx_dma)
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msm_geni_serial_rx_fsm_rst(uport);
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geni_se_rx_dma_unprep(port->wrapper_dev, port->rx_dma,
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DMA_RX_BUF_SIZE);
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port->rx_dma = (dma_addr_t)NULL;
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}
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geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
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IPC_LOG_MSG(port->ipc_log_misc, "%s: 0x%x\n", __func__, geni_status);
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}
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@ -1443,7 +1427,7 @@ static int msm_geni_serial_handle_dma_rx(struct uart_port *uport, bool drop_rx)
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struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
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unsigned int rx_bytes = 0;
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struct tty_port *tport;
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int ret;
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int ret = 0;
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unsigned int geni_status;
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geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
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@ -1451,16 +1435,13 @@ static int msm_geni_serial_handle_dma_rx(struct uart_port *uport, bool drop_rx)
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if (!(geni_status & S_GENI_CMD_ACTIVE))
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return 0;
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geni_se_rx_dma_unprep(msm_port->wrapper_dev, msm_port->rx_dma,
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DMA_RX_BUF_SIZE);
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msm_port->rx_dma = (dma_addr_t)NULL;
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rx_bytes = geni_read_reg_nolog(uport->membase, SE_DMA_RX_LEN_IN);
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if (unlikely(!msm_port->rx_buf)) {
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IPC_LOG_MSG(msm_port->ipc_log_rx, "%s: NULL Rx_buf\n",
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__func__);
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return 0;
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}
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rx_bytes = geni_read_reg_nolog(uport->membase, SE_DMA_RX_LEN_IN);
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if (unlikely(!rx_bytes)) {
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IPC_LOG_MSG(msm_port->ipc_log_rx, "%s: Size %d\n",
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__func__, rx_bytes);
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@ -1482,10 +1463,9 @@ static int msm_geni_serial_handle_dma_rx(struct uart_port *uport, bool drop_rx)
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dump_ipc(msm_port->ipc_log_rx, "DMA Rx", (char *)msm_port->rx_buf, 0,
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rx_bytes);
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exit_handle_dma_rx:
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ret = geni_se_rx_dma_prep(msm_port->wrapper_dev, uport->membase,
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msm_port->rx_buf, DMA_RX_BUF_SIZE, &msm_port->rx_dma);
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if (ret)
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IPC_LOG_MSG(msm_port->ipc_log_rx, "%s: %d\n", __func__, ret);
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geni_se_rx_dma_start(uport->membase, DMA_RX_BUF_SIZE,
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&msm_port->rx_dma);
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return ret;
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}
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@ -1771,6 +1751,7 @@ static int msm_geni_serial_port_setup(struct uart_port *uport)
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int ret = 0;
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struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
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unsigned long cfg0, cfg1;
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dma_addr_t dma_address;
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unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
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set_rfr_wm(msm_port);
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@ -1796,14 +1777,15 @@ static int msm_geni_serial_port_setup(struct uart_port *uport)
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goto exit_portsetup;
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}
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msm_port->rx_buf = devm_kzalloc(uport->dev, DMA_RX_BUF_SIZE,
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GFP_KERNEL);
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msm_port->rx_buf = dma_alloc_coherent(msm_port->wrapper_dev,
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DMA_RX_BUF_SIZE, &dma_address, GFP_KERNEL);
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if (!msm_port->rx_buf) {
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devm_kfree(uport->dev, msm_port->rx_fifo);
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msm_port->rx_fifo = NULL;
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ret = -ENOMEM;
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goto exit_portsetup;
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}
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msm_port->rx_dma = dma_address;
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} else {
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/*
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* Make an unconditional cancel on the main sequencer to reset
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@ -1825,12 +1807,12 @@ static int msm_geni_serial_port_setup(struct uart_port *uport)
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ret = geni_se_init(uport->membase, msm_port->rx_wm, msm_port->rx_rfr);
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if (ret) {
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dev_err(uport->dev, "%s: Fail\n", __func__);
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goto exit_portsetup;
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goto free_dma;
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}
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ret = geni_se_select_mode(uport->membase, msm_port->xfer_mode);
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if (ret)
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goto exit_portsetup;
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goto free_dma;
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msm_port->port_setup = true;
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/*
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@ -1838,6 +1820,14 @@ static int msm_geni_serial_port_setup(struct uart_port *uport)
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* framework.
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*/
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mb();
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return 0;
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free_dma:
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if (msm_port->rx_dma) {
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dma_free_coherent(msm_port->wrapper_dev, DMA_RX_BUF_SIZE,
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msm_port->rx_buf, msm_port->rx_dma);
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msm_port->rx_dma = (dma_addr_t)NULL;
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}
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exit_portsetup:
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return ret;
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}
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@ -2806,6 +2796,11 @@ static int msm_geni_serial_remove(struct platform_device *pdev)
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if (!uart_console(&port->uport))
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wakeup_source_unregister(port->geni_wake);
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uart_remove_one_port(drv, &port->uport);
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if (port->rx_dma) {
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dma_free_coherent(port->wrapper_dev, DMA_RX_BUF_SIZE,
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port->rx_buf, port->rx_dma);
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port->rx_dma = (dma_addr_t)NULL;
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}
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return 0;
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}
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LINUX_MSM_GENI_SE
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@ -665,6 +665,19 @@ int geni_se_clk_freq_match(struct se_geni_rsc *rsc, unsigned long req_freq,
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int geni_se_tx_dma_prep(struct device *wrapper_dev, void __iomem *base,
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void *tx_buf, int tx_len, dma_addr_t *tx_dma);
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/**
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* geni_se_rx_dma_start() - Prepare the Serial Engine registers for RX DMA
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transfers.
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* @base: Base address of the SE register block.
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* @rx_len: Length of the RX buffer.
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* @rx_dma: Pointer to store the mapped DMA address.
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*
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* This function is used to prepare the Serial Engine registers for DMA RX.
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*
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* Return: None.
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*/
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void geni_se_rx_dma_start(void __iomem *base, int rx_len, dma_addr_t *rx_dma);
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/**
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* geni_se_rx_dma_prep() - Prepare the Serial Engine for RX DMA transfer
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* @wrapper_dev: QUPv3 Wrapper Device to which the TX buffer is mapped.
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@ -979,5 +992,10 @@ static void geni_se_dump_dbg_regs(struct se_geni_rsc *rsc, void __iomem *base,
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{
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}
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static void geni_se_rx_dma_start(void __iomem *base, int rx_len,
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dma_addr_t *rx_dma)
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{
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}
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#endif
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#endif
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