icc: dt-bindings: add endpoint IDs for interconnects for HOLI

Add master and slave ID constants for all Qualcomm Technologies, Inc.
Holi interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: Icb430597694cebbed32d8d65ef0cd050b82cdeb5
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>

include/dt-bindings/interconnect/qcom,holi.h

@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_HOLI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_HOLI_H
+
+#define MASTER_AMPSS_M0		0
+#define MASTER_SNOC_BIMC_RT		1
+#define MASTER_SNOC_BIMC_NRT		2
+#define MASTER_SNOC_BIMC		3
+#define MASTER_GPU_CDSP_PROC		4
+#define MASTER_TCU_0		5
+#define MASTER_SNOC_CNOC		6
+#define MASTER_QDSS_DAP		7
+#define MASTER_CRYPTO		8
+#define MASTER_QUP_CORE_0		9
+#define MASTER_QUP_CORE_1		10
+#define MASTER_SNOC_CFG		12
+#define MASTER_TIC		12
+#define MASTER_ANOC_SNOC		13
+#define MASTER_CAMNOC_SF		14
+#define MASTER_CAMNOC_HF		15
+#define MASTER_BIMC_SNOC		16
+#define MASTER_MDP_PORT0		17
+#define MASTER_PIMEM		18
+#define MASTER_VIDEO_P0		19
+#define MASTER_VIDEO_PROC		20
+#define MASTER_QDSS_BAM		22
+#define MASTER_QUP_0		22
+#define MASTER_QUP_1		23
+#define MASTER_IPA		24
+#define MASTER_QDSS_ETR		25
+#define MASTER_SDCC_1		26
+#define MASTER_SDCC_2		27
+#define MASTER_UFS_MEM		28
+#define MASTER_USB3		29
+#define MASTER_GRAPHICS_3D_PORT1		30
+#define MASTER_GRAPHICS_3D		31
+#define SLAVE_EBI		32
+#define SLAVE_BIMC_SNOC		33
+#define SLAVE_BIMC_CFG		34
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG		35
+#define SLAVE_CAMERA_RT_THROTTLE_CFG		36
+#define SLAVE_CAMERA_CFG		37
+#define SLAVE_CDSP_THROTTLE_CFG		38
+#define SLAVE_CLK_CTL		39
+#define SLAVE_CRYPTO_0_CFG		40
+#define SLAVE_DISPLAY_CFG		41
+#define SLAVE_DISPLAY_THROTTLE_CFG		42
+#define SLAVE_GPU_CFG		43
+#define SLAVE_IMEM_CFG		44
+#define SLAVE_IPA_CFG		45
+#define SLAVE_LPASS		46
+#define SLAVE_MESSAGE_RAM		47
+#define SLAVE_PDM		48
+#define SLAVE_PIMEM_CFG		49
+#define SLAVE_PMIC_ARB		50
+#define SLAVE_PRNG		51
+#define SLAVE_QDSS_CFG		52
+#define SLAVE_QM_CFG		53
+#define SLAVE_QM_MPU_CFG		54
+#define SLAVE_QUP_0		55
+#define SLAVE_QUP_1		56
+#define SLAVE_SDCC_1		57
+#define SLAVE_SDCC_2		58
+#define SLAVE_SNOC_CFG		59
+#define SLAVE_TCSR		60
+#define SLAVE_TLMM_EAST		61
+#define SLAVE_TLMM_SOUTH		62
+#define SLAVE_TLMM_WEST		63
+#define SLAVE_UFS_MEM_CFG		64
+#define SLAVE_USB3		65
+#define SLAVE_VENUS_CFG		66
+#define SLAVE_VENUS_THROTTLE_CFG		67
+#define SLAVE_VSENSE_CTRL_CFG		68
+#define SLAVE_SERVICE_CNOC		69
+#define SLAVE_QUP_CORE_0		70
+#define SLAVE_QUP_CORE_1		71
+#define SLAVE_APPSS		72
+#define SLAVE_SNOC_BIMC_NRT		73
+#define SLAVE_SNOC_BIMC_RT		74
+#define SLAVE_SNOC_CNOC		75
+#define SLAVE_OCIMEM		76
+#define SLAVE_PIMEM		77
+#define SLAVE_SNOC_BIMC		78
+#define SLAVE_SERVICE_SNOC		79
+#define SLAVE_QDSS_STM		80
+#define SLAVE_TCU		81
+#define SLAVE_ANOC_SNOC		82
+#define SLAVE_GPU_CDSP_BIMC		83
+
+#endif