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iommu: arm-smmu: optimize arch write sync delay

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With ARM_SMMU_POWER_ALWAYS_ON enabled, clocks are always on. There arch
write sync is not required. Move arch write sync post checking for clock
refcount.
Arch write sync takes longer due to virtualized global register read. Use
non virtuazlied global register to reduce read latency.

Change-Id: Ic497c7ba75cc8ba2ed804f2c987e0c595487ce40
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
This commit is contained in:
Prakash Gupta 2021-01-20 14:10:21 +05:30
commit c802bb3a23
1 changed files with 3 additions and 3 deletions
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6
drivers/iommu/arm-smmu.c
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@ -365,7 +365,8 @@ static void arm_smmu_arch_write_sync(struct arm_smmu_device *smmu)
return;
/* Read to complete prior write transcations */
id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0);
id = arm_smmu_readl(smmu, ARM_SMMU_IMPL_DEF0, 0);
/* Wait for read to complete before off */
rmb();
@ -656,8 +657,6 @@ static void arm_smmu_power_off_atomic(struct arm_smmu_device *smmu,
{
unsigned long flags;
arm_smmu_arch_write_sync(smmu);
spin_lock_irqsave(&pwr->clock_refs_lock, flags);
if (pwr->clock_refs_count == 0) {
WARN(1, "%s: bad clock_ref_count\n", dev_name(pwr->dev));
@ -670,6 +669,7 @@ static void arm_smmu_power_off_atomic(struct arm_smmu_device *smmu,
return;
}
arm_smmu_arch_write_sync(smmu);
arm_smmu_disable_clocks(pwr);
pwr->clock_refs_count = 0;