diff --git a/drivers/gpu/msm/a6xx_reg.h b/drivers/gpu/msm/a6xx_reg.h index a2b83f15809f..b3b7f2e5ce1b 100644 --- a/drivers/gpu/msm/a6xx_reg.h +++ b/drivers/gpu/msm/a6xx_reg.h @@ -1122,7 +1122,7 @@ * now we are using a separate section for RSCC regsiters. Add the * offset for backward compatibility. */ -#define RSCC_OFFSET_LEGACY 0x23400 +#define RSCC_OFFSET_LEGACY 0x23000 /* RGMU(PCC) registers in A6X_GMU_CX_0_NON_CONTEXT_DEC domain */ #define A6XX_RGMU_CX_INTR_GEN_EN 0x1F80F diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 8e01c1c20224..46fb0735c173 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1110,25 +1110,6 @@ static void adreno_cx_misc_probe(struct kgsl_device *device) res->start, adreno_dev->cx_misc_len); } -static void adreno_rscc_probe(struct kgsl_device *device) -{ - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - struct resource *res; - - res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM, - "rscc"); - - if (res == NULL) - return; - - adreno_dev->rscc_base = res->start - device->reg_phys; - adreno_dev->rscc_len = resource_size(res); - adreno_dev->rscc_virt = devm_ioremap(&device->pdev->dev, res->start, - adreno_dev->rscc_len); - if (adreno_dev->rscc_virt == NULL) - dev_warn(device->dev, "rscc ioremap failed\n"); -} - static void adreno_isense_probe(struct kgsl_device *device) { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); @@ -1379,8 +1360,6 @@ int adreno_device_probe(struct platform_device *pdev, /* Probe for the optional CX_MISC block */ adreno_cx_misc_probe(device); - adreno_rscc_probe(device); - adreno_isense_probe(device); /* Allocate the memstore for storing timestamps and other useful info */ @@ -3144,24 +3123,6 @@ void adreno_cx_misc_regread(struct adreno_device *adreno_dev, */ rmb(); } -void adreno_rscc_regread(struct adreno_device *adreno_dev, - unsigned int offsetwords, unsigned int *value) -{ - unsigned int rscc_offset; - - rscc_offset = (offsetwords << 2); - if (!adreno_dev->rscc_virt || - (rscc_offset >= adreno_dev->rscc_len)) - return; - - *value = __raw_readl(adreno_dev->rscc_virt + rscc_offset); - - /* - * ensure this read finishes before the next one. - * i.e. act like normal readl() - */ - rmb(); -} void adreno_isense_regread(struct adreno_device *adreno_dev, unsigned int offsetwords, unsigned int *value) diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 0decb1041d54..8e5229d7df51 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -405,9 +405,6 @@ struct adreno_gpu_core { * @chipid: Chip ID specific to the GPU * @cx_misc_len: Length of the CX MISC register block * @cx_misc_virt: Pointer where the CX MISC block is mapped - * @rscc_base: Base physical address of the RSCC - * @rscc_len: Length of the RSCC register block - * @rscc_virt: Pointer where RSCC block is mapped * @isense_base: Base physical address of isense block * @isense_len: Length of the isense register block * @isense_virt: Pointer where isense block is mapped @@ -487,9 +484,6 @@ struct adreno_device { void __iomem *cx_dbgc_virt; unsigned int cx_misc_len; void __iomem *cx_misc_virt; - unsigned long rscc_base; - unsigned int rscc_len; - void __iomem *rscc_virt; unsigned long isense_base; unsigned int isense_len; void __iomem *isense_virt; @@ -978,8 +972,6 @@ void adreno_cx_misc_regwrite(struct adreno_device *adreno_dev, void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev, unsigned int offsetwords, unsigned int mask, unsigned int bits); -void adreno_rscc_regread(struct adreno_device *adreno_dev, - unsigned int offsetwords, unsigned int *value); void adreno_isense_regread(struct adreno_device *adreno_dev, unsigned int offsetwords, unsigned int *value); diff --git a/drivers/gpu/msm/adreno_a6xx.h b/drivers/gpu/msm/adreno_a6xx.h index 40e0b222cdd6..3af126c6be78 100644 --- a/drivers/gpu/msm/adreno_a6xx.h +++ b/drivers/gpu/msm/adreno_a6xx.h @@ -224,39 +224,6 @@ static inline int timed_poll_check(struct kgsl_device *device, return 0; } -static inline int timed_poll_check_rscc(struct kgsl_device *device, - unsigned int offset, unsigned int expected_ret, - unsigned int timeout, unsigned int mask) -{ - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - unsigned long t; - unsigned int value; - - if (!adreno_is_a650_family(adreno_dev)) - return timed_poll_check(device, offset + RSCC_OFFSET_LEGACY, - expected_ret, timeout, mask); - - t = jiffies + msecs_to_jiffies(timeout); - - do { - adreno_rscc_regread(adreno_dev, offset, &value); - - if ((value & mask) == expected_ret) - return 0; - /* Wait 100us to reduce unnecessary AHB bus traffic */ - usleep_range(10, 100); - } while (!time_after(jiffies, t)); - - /* Double check one last time */ - if (adreno_is_a650_family(adreno_dev)) - adreno_rscc_regread(adreno_dev, offset, &value); - - if ((value & mask) == expected_ret) - return 0; - - return -ETIMEDOUT; -} - /* Preemption functions */ void a6xx_preemption_trigger(struct adreno_device *adreno_dev); void a6xx_preemption_schedule(struct adreno_device *adreno_dev); diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 5b770f8a9422..3ce035f7a85a 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -102,6 +102,22 @@ static struct gmu_iommu_context a6xx_gmu_ctx[] = { [GMU_CONTEXT_KERNEL] = { .name = "gmu_kernel" } }; +static int timed_poll_check_rscc(struct kgsl_device *device, + unsigned int offset, unsigned int expected_ret, + unsigned int timeout, unsigned int mask) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); + u32 value; + + if (!adreno_is_a650_family(adreno_dev)) + return timed_poll_check(device, offset + RSCC_OFFSET_LEGACY, + expected_ret, timeout, mask); + + return readl_poll_timeout(gmu->rscc_virt + (offset << 2), value, + (value & mask) == expected_ret, 100, timeout * 1000); +} + void gmu_fault_snapshot(struct kgsl_device *device) { device->gmu_fault = true; @@ -139,10 +155,11 @@ static void _regwrite(void __iomem *regbase, static void a6xx_load_rsc_ucode(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); + struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); void __iomem *rscc; if (adreno_is_a650_family(adreno_dev)) - rscc = adreno_dev->rscc_virt; + rscc = gmu->rscc_virt; else rscc = device->gmu_core.reg_virt + 0x23000; @@ -2062,11 +2079,6 @@ static int a6xx_gmu_first_boot(struct adreno_device *adreno_dev) struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); int level, ret; - if (adreno_is_a650_family(adreno_dev) && !adreno_dev->rscc_virt) { - dev_err(&gmu->pdev->dev, "RSCC registers not mapped\n"); - return -EINVAL; - } - ret = a6xx_gmu_aop_send_acd_state(gmu->mailbox.channel, adreno_dev->acd_enabled); if (ret) { @@ -2552,6 +2564,7 @@ static int a6xx_gmu_probe(struct kgsl_device *device, struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); struct a6xx_hfi *hfi = &gmu->hfi; + struct resource *res; int ret; gmu->pdev = pdev; @@ -2560,6 +2573,17 @@ static int a6xx_gmu_probe(struct kgsl_device *device, gmu->pdev->dev.dma_mask = &gmu->pdev->dev.coherent_dma_mask; set_dma_ops(&gmu->pdev->dev, NULL); + res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM, + "rscc"); + if (res) { + gmu->rscc_virt = devm_ioremap(&device->pdev->dev, res->start, + resource_size(res)); + if (gmu->rscc_virt == NULL) { + dev_err(&gmu->pdev->dev, "rscc ioremap failed\n"); + return -ENOMEM; + } + } + /* Set up GMU regulators */ ret = a6xx_gmu_regulators_probe(gmu, pdev); if (ret) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.h b/drivers/gpu/msm/adreno_a6xx_gmu.h index 9a3341c06b75..e6bdc5f49d60 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.h +++ b/drivers/gpu/msm/adreno_a6xx_gmu.h @@ -201,6 +201,8 @@ struct a6xx_gmu_device { void *itcm_shadow; /** @flags: Internal gmu flags */ unsigned long flags; + /** @rscc_virt: Pointer where RSCC block is mapped */ + void __iomem *rscc_virt; }; /* Helper function to get to a6xx gmu device from adreno device */ diff --git a/drivers/gpu/msm/adreno_a6xx_gmu_snapshot.c b/drivers/gpu/msm/adreno_a6xx_gmu_snapshot.c index bdecffdec328..8ec0951108f3 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu_snapshot.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu_snapshot.c @@ -57,6 +57,74 @@ static const unsigned int a660_gmu_registers[] = { 0x20018, 0x20018, }; +static const unsigned int a630_rscc_snapshot_registers[] = { + 0x23400, 0x23434, 0x23436, 0x23436, 0x23480, 0x23484, 0x23489, 0x2348C, + 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, + 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, + 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, + 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, + 0x2393C, 0x2393F, 0x23944, 0x2397F, +}; + +static const unsigned int a6xx_rscc_snapshot_registers[] = { + 0x23400, 0x23434, 0x23436, 0x23436, 0x23440, 0x23440, 0x23480, 0x23484, + 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, + 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, + 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, + 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, + 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, +}; + +static const unsigned int a650_rscc_registers[] = { + 0x38000, 0x38034, 0x38036, 0x38036, 0x38040, 0x38042, 0x38080, 0x38084, + 0x38089, 0x3808C, 0x38091, 0x38094, 0x38099, 0x3809C, 0x380A1, 0x380A4, + 0x380A9, 0x380AC, 0x38100, 0x38102, 0x38104, 0x38107, 0x38114, 0x38119, + 0x38124, 0x3812E, 0x38180, 0x38197, 0x38340, 0x38341, 0x38344, 0x38347, + 0x3834C, 0x3834F, 0x38351, 0x38354, 0x38356, 0x38359, 0x3835B, 0x3835E, + 0x38360, 0x38363, 0x38365, 0x38368, 0x3836A, 0x3836D, 0x3836F, 0x38372, + 0x383EC, 0x383EF, 0x383F4, 0x383F7, 0x383F9, 0x383FC, 0x383FE, 0x38401, + 0x38403, 0x38406, 0x38408, 0x3840B, 0x3840D, 0x38410, 0x38412, 0x38415, + 0x38417, 0x3841A, 0x38494, 0x38497, 0x3849C, 0x3849F, 0x384A1, 0x384A4, + 0x384A6, 0x384A9, 0x384AB, 0x384AE, 0x384B0, 0x384B3, 0x384B5, 0x384B8, + 0x384BA, 0x384BD, 0x384BF, 0x384C2, 0x3853C, 0x3853F, 0x38544, 0x38547, + 0x38549, 0x3854C, 0x3854E, 0x38551, 0x38553, 0x38556, 0x38558, 0x3855B, + 0x3855D, 0x38560, 0x38562, 0x38565, 0x38567, 0x3856A, 0x385E4, 0x385E7, + 0x385EC, 0x385EF, 0x385F1, 0x385F4, 0x385F6, 0x385F9, 0x385FB, 0x385FE, + 0x38600, 0x38603, 0x38605, 0x38608, 0x3860A, 0x3860D, 0x3860F, 0x38612, + 0x3868C, 0x3868F, 0x38694, 0x38697, 0x38699, 0x3869C, 0x3869E, 0x386A1, + 0x386A3, 0x386A6, 0x386A8, 0x386AB, 0x386AD, 0x386B0, 0x386B2, 0x386B5, + 0x386B7, 0x386BA, 0x38734, 0x38737, 0x3873C, 0x3873F, 0x38741, 0x38744, + 0x38746, 0x38749, 0x3874B, 0x3874E, 0x38750, 0x38753, 0x38755, 0x38758, + 0x3875A, 0x3875D, 0x3875F, 0x38762, 0x387DC, 0x387DF, 0x387E4, 0x387E7, + 0x387E9, 0x387EC, 0x387EE, 0x387F1, 0x387F3, 0x387F6, 0x387F8, 0x387FB, + 0x387FD, 0x38800, 0x38802, 0x38805, 0x38807, 0x3880A, 0x38884, 0x38887, + 0x3888C, 0x3888F, 0x38891, 0x38894, 0x38896, 0x38899, 0x3889B, 0x3889E, + 0x388A0, 0x388A3, 0x388A5, 0x388A8, 0x388AA, 0x388AD, 0x388AF, 0x388B2, + 0x3892C, 0x3892F, 0x38934, 0x38937, 0x38939, 0x3893C, 0x3893E, 0x38941, + 0x38943, 0x38946, 0x38948, 0x3894B, 0x3894D, 0x38950, 0x38952, 0x38955, + 0x38957, 0x3895A, 0x38B50, 0x38B51, 0x38B53, 0x38B55, 0x38B5A, 0x38B5A, + 0x38B5F, 0x38B5F, 0x38B64, 0x38B64, 0x38B69, 0x38B69, 0x38B6E, 0x38B6E, + 0x38B73, 0x38B73, 0x38BF8, 0x38BF8, 0x38BFD, 0x38BFD, 0x38C02, 0x38C02, + 0x38C07, 0x38C07, 0x38C0C, 0x38C0C, 0x38C11, 0x38C11, 0x38C16, 0x38C16, + 0x38C1B, 0x38C1B, 0x38CA0, 0x38CA0, 0x38CA5, 0x38CA5, 0x38CAA, 0x38CAA, + 0x38CAF, 0x38CAF, 0x38CB4, 0x38CB4, 0x38CB9, 0x38CB9, 0x38CBE, 0x38CBE, + 0x38CC3, 0x38CC3, 0x38D48, 0x38D48, 0x38D4D, 0x38D4D, 0x38D52, 0x38D52, + 0x38D57, 0x38D57, 0x38D5C, 0x38D5C, 0x38D61, 0x38D61, 0x38D66, 0x38D66, + 0x38D6B, 0x38D6B, 0x38DF0, 0x38DF0, 0x38DF5, 0x38DF5, 0x38DFA, 0x38DFA, + 0x38DFF, 0x38DFF, 0x38E04, 0x38E04, 0x38E09, 0x38E09, 0x38E0E, 0x38E0E, + 0x38E13, 0x38E13, 0x38E98, 0x38E98, 0x38E9D, 0x38E9D, 0x38EA2, 0x38EA2, + 0x38EA7, 0x38EA7, 0x38EAC, 0x38EAC, 0x38EB1, 0x38EB1, 0x38EB6, 0x38EB6, + 0x38EBB, 0x38EBB, 0x38F40, 0x38F40, 0x38F45, 0x38F45, 0x38F4A, 0x38F4A, + 0x38F4F, 0x38F4F, 0x38F54, 0x38F54, 0x38F59, 0x38F59, 0x38F5E, 0x38F5E, + 0x38F63, 0x38F63, 0x38FE8, 0x38FE8, 0x38FED, 0x38FED, 0x38FF2, 0x38FF2, + 0x38FF7, 0x38FF7, 0x38FFC, 0x38FFC, 0x39001, 0x39001, 0x39006, 0x39006, + 0x3900B, 0x3900B, 0x39090, 0x39090, 0x39095, 0x39095, 0x3909A, 0x3909A, + 0x3909F, 0x3909F, 0x390A4, 0x390A4, 0x390A9, 0x390A9, 0x390AE, 0x390AE, + 0x390B3, 0x390B3, 0x39138, 0x39138, 0x3913D, 0x3913D, 0x39142, 0x39142, + 0x39147, 0x39147, 0x3914C, 0x3914C, 0x39151, 0x39151, 0x39156, 0x39156, + 0x3915B, 0x3915B, +}; + struct gmu_mem_type_desc { struct gmu_memdesc *memdesc; uint32_t type; @@ -225,6 +293,77 @@ static void a6xx_gmu_snapshot_versions(struct kgsl_device *device, &gmu_vers[i]); } +#define RSCC_OFFSET_DWORDS 0x38000 + +static size_t a6xx_snapshot_rscc_registers(struct kgsl_device *device, u8 *buf, + size_t remain, void *priv) +{ + struct kgsl_snapshot_regs *header = (struct kgsl_snapshot_regs *)buf; + struct kgsl_snapshot_registers *regs = priv; + unsigned int *data = (unsigned int *)(buf + sizeof(*header)); + int count = 0, j, k; + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); + + /* Figure out how many registers we are going to dump */ + for (j = 0; j < regs->count; j++) { + int start = regs->regs[j * 2]; + int end = regs->regs[j * 2 + 1]; + + count += (end - start + 1); + } + + if (remain < (count * 8) + sizeof(*header)) { + SNAPSHOT_ERR_NOMEM(device, "RSCC REGISTERS"); + return 0; + } + + for (j = 0; j < regs->count; j++) { + unsigned int start = regs->regs[j * 2]; + unsigned int end = regs->regs[j * 2 + 1]; + + for (k = start; k <= end; k++) { + unsigned int val; + + val = __raw_readl(gmu->rscc_virt + + ((k - RSCC_OFFSET_DWORDS) << 2)); + *data++ = k; + *data++ = val; + } + } + + header->count = count; + + /* Return the size of the section */ + return (count * 8) + sizeof(*header); +} + +static void snapshot_rscc_registers(struct adreno_device *adreno_dev, + struct kgsl_snapshot *snapshot) +{ + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); + + /* RSCC registers are on cx */ + if (adreno_is_a650_family(adreno_dev)) { + struct kgsl_snapshot_registers r; + + r.regs = a650_rscc_registers; + r.count = ARRAY_SIZE(a650_rscc_registers) / 2; + + kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, + snapshot, a6xx_snapshot_rscc_registers, &r); + } else if (adreno_is_a615_family(adreno_dev) || + adreno_is_a630(adreno_dev)) { + adreno_snapshot_registers(device, snapshot, + a630_rscc_snapshot_registers, + ARRAY_SIZE(a630_rscc_snapshot_registers) / 2); + } else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { + adreno_snapshot_registers(device, snapshot, + a6xx_rscc_snapshot_registers, + ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2); + } +} + /* * a6xx_gmu_device_snapshot() - A6XX GMU snapshot function * @device: Device being snapshotted @@ -236,7 +375,8 @@ static void a6xx_gmu_snapshot_versions(struct kgsl_device *device, void a6xx_gmu_device_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { - struct a6xx_gmu_device *gmu = to_a6xx_gmu(ADRENO_DEVICE(device)); + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); unsigned int val; kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_GMU_MEMORY, @@ -250,8 +390,8 @@ void a6xx_gmu_device_snapshot(struct kgsl_device *device, a6xx_gmu_snapshot_memories(device, gmu, snapshot); /* Snapshot tcms as registers for legacy targets */ - if (adreno_is_a630(ADRENO_DEVICE(device)) || - adreno_is_a615_family(ADRENO_DEVICE(device))) + if (adreno_is_a630(adreno_dev) || + adreno_is_a615_family(adreno_dev)) adreno_snapshot_registers(device, snapshot, a6xx_gmu_tcm_registers, ARRAY_SIZE(a6xx_gmu_tcm_registers) / 2); @@ -260,10 +400,12 @@ void a6xx_gmu_device_snapshot(struct kgsl_device *device, ARRAY_SIZE(a6xx_gmu_registers) / 2); /* Snapshot A660 specific GMU registers */ - if (adreno_is_a660(ADRENO_DEVICE(device))) + if (adreno_is_a660(adreno_dev)) adreno_snapshot_registers(device, snapshot, a660_gmu_registers, ARRAY_SIZE(a660_gmu_registers) / 2); + snapshot_rscc_registers(adreno_dev, snapshot); + if (!a6xx_gmu_gx_is_on(device)) return; diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c index 7181c6ca574a..23f20f2802a2 100644 --- a/drivers/gpu/msm/adreno_a6xx_snapshot.c +++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c @@ -46,74 +46,6 @@ static const unsigned int a6xx_pc_vs_cluster[] = { 0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9B00, 0x9B07, }; -static const unsigned int a630_rscc_snapshot_registers[] = { - 0x23400, 0x23434, 0x23436, 0x23436, 0x23480, 0x23484, 0x23489, 0x2348C, - 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, 0x234A9, 0x234AC, - 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, 0x23524, 0x2352B, - 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, 0x2374C, 0x23787, - 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, 0x2389C, 0x238D7, - 0x2393C, 0x2393F, 0x23944, 0x2397F, -}; - -static const unsigned int a6xx_rscc_snapshot_registers[] = { - 0x23400, 0x23434, 0x23436, 0x23436, 0x23440, 0x23440, 0x23480, 0x23484, - 0x23489, 0x2348C, 0x23491, 0x23494, 0x23499, 0x2349C, 0x234A1, 0x234A4, - 0x234A9, 0x234AC, 0x23500, 0x23502, 0x23504, 0x23507, 0x23514, 0x23519, - 0x23524, 0x2352B, 0x23580, 0x23597, 0x23740, 0x23741, 0x23744, 0x23747, - 0x2374C, 0x23787, 0x237EC, 0x237EF, 0x237F4, 0x2382F, 0x23894, 0x23897, - 0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F, -}; - -static const unsigned int a650_rscc_registers[] = { - 0x38000, 0x38034, 0x38036, 0x38036, 0x38040, 0x38042, 0x38080, 0x38084, - 0x38089, 0x3808C, 0x38091, 0x38094, 0x38099, 0x3809C, 0x380A1, 0x380A4, - 0x380A9, 0x380AC, 0x38100, 0x38102, 0x38104, 0x38107, 0x38114, 0x38119, - 0x38124, 0x3812E, 0x38180, 0x38197, 0x38340, 0x38341, 0x38344, 0x38347, - 0x3834C, 0x3834F, 0x38351, 0x38354, 0x38356, 0x38359, 0x3835B, 0x3835E, - 0x38360, 0x38363, 0x38365, 0x38368, 0x3836A, 0x3836D, 0x3836F, 0x38372, - 0x383EC, 0x383EF, 0x383F4, 0x383F7, 0x383F9, 0x383FC, 0x383FE, 0x38401, - 0x38403, 0x38406, 0x38408, 0x3840B, 0x3840D, 0x38410, 0x38412, 0x38415, - 0x38417, 0x3841A, 0x38494, 0x38497, 0x3849C, 0x3849F, 0x384A1, 0x384A4, - 0x384A6, 0x384A9, 0x384AB, 0x384AE, 0x384B0, 0x384B3, 0x384B5, 0x384B8, - 0x384BA, 0x384BD, 0x384BF, 0x384C2, 0x3853C, 0x3853F, 0x38544, 0x38547, - 0x38549, 0x3854C, 0x3854E, 0x38551, 0x38553, 0x38556, 0x38558, 0x3855B, - 0x3855D, 0x38560, 0x38562, 0x38565, 0x38567, 0x3856A, 0x385E4, 0x385E7, - 0x385EC, 0x385EF, 0x385F1, 0x385F4, 0x385F6, 0x385F9, 0x385FB, 0x385FE, - 0x38600, 0x38603, 0x38605, 0x38608, 0x3860A, 0x3860D, 0x3860F, 0x38612, - 0x3868C, 0x3868F, 0x38694, 0x38697, 0x38699, 0x3869C, 0x3869E, 0x386A1, - 0x386A3, 0x386A6, 0x386A8, 0x386AB, 0x386AD, 0x386B0, 0x386B2, 0x386B5, - 0x386B7, 0x386BA, 0x38734, 0x38737, 0x3873C, 0x3873F, 0x38741, 0x38744, - 0x38746, 0x38749, 0x3874B, 0x3874E, 0x38750, 0x38753, 0x38755, 0x38758, - 0x3875A, 0x3875D, 0x3875F, 0x38762, 0x387DC, 0x387DF, 0x387E4, 0x387E7, - 0x387E9, 0x387EC, 0x387EE, 0x387F1, 0x387F3, 0x387F6, 0x387F8, 0x387FB, - 0x387FD, 0x38800, 0x38802, 0x38805, 0x38807, 0x3880A, 0x38884, 0x38887, - 0x3888C, 0x3888F, 0x38891, 0x38894, 0x38896, 0x38899, 0x3889B, 0x3889E, - 0x388A0, 0x388A3, 0x388A5, 0x388A8, 0x388AA, 0x388AD, 0x388AF, 0x388B2, - 0x3892C, 0x3892F, 0x38934, 0x38937, 0x38939, 0x3893C, 0x3893E, 0x38941, - 0x38943, 0x38946, 0x38948, 0x3894B, 0x3894D, 0x38950, 0x38952, 0x38955, - 0x38957, 0x3895A, 0x38B50, 0x38B51, 0x38B53, 0x38B55, 0x38B5A, 0x38B5A, - 0x38B5F, 0x38B5F, 0x38B64, 0x38B64, 0x38B69, 0x38B69, 0x38B6E, 0x38B6E, - 0x38B73, 0x38B73, 0x38BF8, 0x38BF8, 0x38BFD, 0x38BFD, 0x38C02, 0x38C02, - 0x38C07, 0x38C07, 0x38C0C, 0x38C0C, 0x38C11, 0x38C11, 0x38C16, 0x38C16, - 0x38C1B, 0x38C1B, 0x38CA0, 0x38CA0, 0x38CA5, 0x38CA5, 0x38CAA, 0x38CAA, - 0x38CAF, 0x38CAF, 0x38CB4, 0x38CB4, 0x38CB9, 0x38CB9, 0x38CBE, 0x38CBE, - 0x38CC3, 0x38CC3, 0x38D48, 0x38D48, 0x38D4D, 0x38D4D, 0x38D52, 0x38D52, - 0x38D57, 0x38D57, 0x38D5C, 0x38D5C, 0x38D61, 0x38D61, 0x38D66, 0x38D66, - 0x38D6B, 0x38D6B, 0x38DF0, 0x38DF0, 0x38DF5, 0x38DF5, 0x38DFA, 0x38DFA, - 0x38DFF, 0x38DFF, 0x38E04, 0x38E04, 0x38E09, 0x38E09, 0x38E0E, 0x38E0E, - 0x38E13, 0x38E13, 0x38E98, 0x38E98, 0x38E9D, 0x38E9D, 0x38EA2, 0x38EA2, - 0x38EA7, 0x38EA7, 0x38EAC, 0x38EAC, 0x38EB1, 0x38EB1, 0x38EB6, 0x38EB6, - 0x38EBB, 0x38EBB, 0x38F40, 0x38F40, 0x38F45, 0x38F45, 0x38F4A, 0x38F4A, - 0x38F4F, 0x38F4F, 0x38F54, 0x38F54, 0x38F59, 0x38F59, 0x38F5E, 0x38F5E, - 0x38F63, 0x38F63, 0x38FE8, 0x38FE8, 0x38FED, 0x38FED, 0x38FF2, 0x38FF2, - 0x38FF7, 0x38FF7, 0x38FFC, 0x38FFC, 0x39001, 0x39001, 0x39006, 0x39006, - 0x3900B, 0x3900B, 0x39090, 0x39090, 0x39095, 0x39095, 0x3909A, 0x3909A, - 0x3909F, 0x3909F, 0x390A4, 0x390A4, 0x390A9, 0x390A9, 0x390AE, 0x390AE, - 0x390B3, 0x390B3, 0x39138, 0x39138, 0x3913D, 0x3913D, 0x39142, 0x39142, - 0x39147, 0x39147, 0x3914C, 0x3914C, 0x39151, 0x39151, 0x39156, 0x39156, - 0x3915B, 0x3915B, -}; - static const unsigned int a650_isense_registers[] = { 0x22C00, 0x22C19, 0x22C26, 0x22C2D, 0x22C2F, 0x22C36, 0x22C40, 0x22C44, 0x22C50, 0x22C57, 0x22C60, 0x22C67, 0x22C80, 0x22C87, 0x22D25, 0x22D2A, @@ -1655,48 +1587,6 @@ static void _a6xx_do_crashdump(struct kgsl_device *device) crash_dump_valid = true; } -static size_t a6xx_snapshot_rscc_registers(struct kgsl_device *device, u8 *buf, - size_t remain, void *priv) -{ - struct kgsl_snapshot_regs *header = (struct kgsl_snapshot_regs *)buf; - struct kgsl_snapshot_registers *regs = priv; - unsigned int *data = (unsigned int *)(buf + sizeof(*header)); - int count = 0, j, k; - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - - /* Figure out how many registers we are going to dump */ - for (j = 0; j < regs->count; j++) { - int start = regs->regs[j * 2]; - int end = regs->regs[j * 2 + 1]; - - count += (end - start + 1); - } - - if (remain < (count * 8) + sizeof(*header)) { - SNAPSHOT_ERR_NOMEM(device, "RSCC REGISTERS"); - return 0; - } - - for (j = 0; j < regs->count; j++) { - unsigned int start = regs->regs[j * 2]; - unsigned int end = regs->regs[j * 2 + 1]; - - for (k = start; k <= end; k++) { - unsigned int val; - - adreno_rscc_regread(adreno_dev, - k - (adreno_dev->rscc_base >> 2), &val); - *data++ = k; - *data++ = val; - } - } - - header->count = count; - - /* Return the size of the section */ - return (count * 8) + sizeof(*header); -} - static size_t a6xx_snapshot_isense_registers(struct kgsl_device *device, u8 *buf, size_t remain, void *priv) { @@ -1797,26 +1687,11 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, if (adreno_is_a650_family(adreno_dev)) { struct kgsl_snapshot_registers r; - r.regs = a650_rscc_registers; - r.count = ARRAY_SIZE(a650_rscc_registers) / 2; - - kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, - snapshot, a6xx_snapshot_rscc_registers, &r); - r.regs = a650_isense_registers; r.count = ARRAY_SIZE(a650_isense_registers) / 2; kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS, snapshot, a6xx_snapshot_isense_registers, &r); - } else if (adreno_is_a615_family(adreno_dev) || - adreno_is_a630(adreno_dev)) { - adreno_snapshot_registers(device, snapshot, - a630_rscc_snapshot_registers, - ARRAY_SIZE(a630_rscc_snapshot_registers) / 2); - } else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { - adreno_snapshot_registers(device, snapshot, - a6xx_rscc_snapshot_registers, - ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2); } else if (adreno_is_a610(adreno_dev)) { adreno_snapshot_registers(device, snapshot, a6xx_gmu_wrapper_registers,