mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
[ARM] 3832/1: iop3xx: coding style cleanup
Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek <[email protected]> Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
475549faa1
commit
c852ac8044
41 changed files with 376 additions and 558 deletions
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@ -1,18 +1,18 @@
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/* linux/include/asm-arm/arch-iop32x/debug-macro.S
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/*
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* include/asm-arm/arch-iop32x/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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*/
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.macro addruart,rx
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mov \rx, #0xfe000000 @ physical
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.macro addruart, rx
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mov \rx, #0xfe000000 @ physical as well as virtual
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orr \rx, \rx, #0x00800000 @ location of the UART
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.endm
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@ -1,7 +1,7 @@
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/*
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* linux/include/asm-arm/arch-iop32x/dma.h
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* include/asm-arm/arch-iop32x/dma.h
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*
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* Copyright (C) 2004 Intel Corp.
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -3,19 +3,16 @@
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*
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* Low-level IRQ helper macros for IOP32x-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/arch/irqs.h>
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#include <asm/arch/iop32x.h>
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.macro disable_fiq
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.macro disable_fiq
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.endm
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/*
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* Note: only deal with normal interrupts, not FIQ
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =IOP3XX_REG_ADDR(0x07D8)
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ldr \irqstat, [\base] @ Read IINTSRC
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cmp \irqstat, #0
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@ -1,8 +1,9 @@
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/*
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* linux/include/asm-arm/arch-iop32x/hardware.h
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* include/asm-arm/arch-iop32x/hardware.h
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#ifndef __HARDWARE_H
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#define __HARDWARE_H
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#include <asm/types.h>
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@ -13,21 +14,23 @@
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* the IO resources.
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*
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* The PCI IO space is located at virtual 0xfe000000 from physical
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* 0x90000000. The PCI BARs must be programmed with physical addresses,
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* but when we read them, we convert them to virtual addresses. See
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* arch/arm/mach-iop3xx/iop3xx-pci.c
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* 0x90000000. The PCI BARs must be programmed with physical addresses,
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* but when we read them, we convert them to virtual addresses. See
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* arch/arm/plat-iop/pci.c.
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*/
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0x00000000
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#define PCIBIOS_MIN_MEM 0x00000000
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#ifndef __ASSEMBLY__
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void iop32x_init_irq(void);
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#endif
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/*
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* Generic chipset bits
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*
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*/
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#include "iop321.h"
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#include "iop32x.h"
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/*
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* Board specific bits
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@ -35,4 +38,5 @@
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#include "iq80321.h"
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#include "iq31244.h"
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#endif /* _ASM_ARCH_HARDWARE_H */
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#endif
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@ -1,21 +1,22 @@
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/*
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* linux/include/asm-arm/arch-iop32x/io.h
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* include/asm-arm/arch-iop32x/io.h
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*
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* Copyright (C) 2001 MontaVista Software, Inc.
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* Copyright (C) 2001 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#ifndef __IO_H
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#define __IO_H
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#include <asm/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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#define IO_SPACE_LIMIT 0xffffffff
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#define __io(p) ((void __iomem *)(p))
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#define __mem_pci(a) (a)
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#endif
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@ -1,86 +0,0 @@
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/*
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* linux/include/asm/arch-iop32x/iop321.h
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*
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* Intel IOP321 Chip definitions
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IOP321_HW_H_
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#define _IOP321_HW_H_
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/*
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* This is needed for mixed drivers that need to work on all
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* IOP3xx variants but behave slightly differently on each.
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*/
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#ifndef __ASSEMBLY__
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#define iop_is_321() 1
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#endif
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/*
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* IOP321 chipset registers
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*/
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#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
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#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
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#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
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/* Reserved 0x00000000 through 0x000000FF */
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/* Address Translation Unit 0x00000100 through 0x000001FF */
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/* Messaging Unit 0x00000300 through 0x000003FF */
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/* DMA Controller 0x00000400 through 0x000004FF */
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/* Memory controller 0x00000500 through 0x0005FF */
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/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
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/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
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/* Internal arbitration unit 0x00000780 through 0x0007BF */
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#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
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#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
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#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
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/* General Purpose I/O Registers */
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#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
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#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
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#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
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/* Interrupt Controller */
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#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
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#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
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#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
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#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
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/* Application accelerator unit 0x00000800 - 0x000008FF */
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/* SSP serial port unit 0x00001600 - 0x0000167F */
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/* I2C bus interface unit 0x00001680 - 0x000016FF */
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/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
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/*
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* Peripherals that are shared between the iop32x and iop33x but
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* located at different addresses.
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*/
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#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
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#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
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#include <asm/hardware/iop3xx.h>
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#ifndef __ASSEMBLY__
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extern void iop321_init_irq(void);
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extern void iop321_time_init(void);
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#endif
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#endif // _IOP321_HW_H_
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28
include/asm-arm/arch-iop32x/iop32x.h
Normal file
28
include/asm-arm/arch-iop32x/iop32x.h
Normal file
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@ -0,0 +1,28 @@
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/*
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* include/asm-arm/arch-iop32x/iop32x.h
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*
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* Intel IOP32X Chip definitions
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __IOP32X_H
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#define __IOP32X_H
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/*
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* Peripherals that are shared between the iop32x and iop33x but
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* located at different addresses.
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*/
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#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
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#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
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#include <asm/hardware/iop3xx.h>
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#endif
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@ -1,11 +1,11 @@
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/*
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* linux/include/asm/arch-iop32x/iq31244.h
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* include/asm-arm/arch-iop32x/iq31244.h
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*
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* Intel IQ31244 evaluation board registers
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*/
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#ifndef _IQ31244_H_
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#define _IQ31244_H_
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#ifndef __IQ31244_H
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#define __IQ31244_H
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#define IQ31244_UART 0xfe800000 /* UART #1 */
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#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
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@ -14,4 +14,4 @@
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#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
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#endif // _IQ31244_H_
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#endif
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@ -1,11 +1,11 @@
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/*
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* linux/include/asm/arch-iop32x/iq80321.h
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* include/asm-arm/arch-iop32x/iq80321.h
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*
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* Intel IQ80321 evaluation board registers
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*/
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#ifndef _IQ80321_H_
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#define _IQ80321_H_
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#ifndef __IQ80321_H
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#define __IQ80321_H
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#define IQ80321_UART 0xfe800000 /* UART #1 */
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#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
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@ -14,4 +14,4 @@
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#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
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#endif // _IQ80321_H_
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#endif
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@ -1,5 +1,5 @@
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/*
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* linux/include/asm-arm/arch-iop32x/irqs.h
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* include/asm-arm/arch-iop32x/irqs.h
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright: (C) 2002 Rory Bolt
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@ -7,44 +7,44 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _IRQS_H_
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#define _IRQS_H_
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#ifndef __IRQS_H
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#define __IRQS_H
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/*
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* IOP80321 chipset interrupts
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*/
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#define IRQ_IOP321_DMA0_EOT 0
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#define IRQ_IOP321_DMA0_EOC 1
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#define IRQ_IOP321_DMA1_EOT 2
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#define IRQ_IOP321_DMA1_EOC 3
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#define IRQ_IOP321_AA_EOT 6
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#define IRQ_IOP321_AA_EOC 7
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#define IRQ_IOP321_CORE_PMON 8
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#define IRQ_IOP321_TIMER0 9
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#define IRQ_IOP321_TIMER1 10
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#define IRQ_IOP321_I2C_0 11
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#define IRQ_IOP321_I2C_1 12
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#define IRQ_IOP321_MESSAGING 13
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#define IRQ_IOP321_ATU_BIST 14
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#define IRQ_IOP321_PERFMON 15
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#define IRQ_IOP321_CORE_PMU 16
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#define IRQ_IOP321_BIU_ERR 17
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#define IRQ_IOP321_ATU_ERR 18
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#define IRQ_IOP321_MCU_ERR 19
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#define IRQ_IOP321_DMA0_ERR 20
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#define IRQ_IOP321_DMA1_ERR 21
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#define IRQ_IOP321_AA_ERR 23
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#define IRQ_IOP321_MSG_ERR 24
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#define IRQ_IOP321_SSP 25
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#define IRQ_IOP321_XINT0 27
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#define IRQ_IOP321_XINT1 28
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#define IRQ_IOP321_XINT2 29
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#define IRQ_IOP321_XINT3 30
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#define IRQ_IOP321_HPI 31
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#define IRQ_IOP32X_DMA0_EOT 0
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#define IRQ_IOP32X_DMA0_EOC 1
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#define IRQ_IOP32X_DMA1_EOT 2
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#define IRQ_IOP32X_DMA1_EOC 3
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#define IRQ_IOP32X_AA_EOT 6
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#define IRQ_IOP32X_AA_EOC 7
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#define IRQ_IOP32X_CORE_PMON 8
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#define IRQ_IOP32X_TIMER0 9
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#define IRQ_IOP32X_TIMER1 10
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#define IRQ_IOP32X_I2C_0 11
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#define IRQ_IOP32X_I2C_1 12
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#define IRQ_IOP32X_MESSAGING 13
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#define IRQ_IOP32X_ATU_BIST 14
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#define IRQ_IOP32X_PERFMON 15
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#define IRQ_IOP32X_CORE_PMU 16
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#define IRQ_IOP32X_BIU_ERR 17
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#define IRQ_IOP32X_ATU_ERR 18
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#define IRQ_IOP32X_MCU_ERR 19
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#define IRQ_IOP32X_DMA0_ERR 20
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#define IRQ_IOP32X_DMA1_ERR 21
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#define IRQ_IOP32X_AA_ERR 23
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#define IRQ_IOP32X_MSG_ERR 24
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#define IRQ_IOP32X_SSP 25
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#define IRQ_IOP32X_XINT0 27
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#define IRQ_IOP32X_XINT1 28
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#define IRQ_IOP32X_XINT2 29
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#define IRQ_IOP32X_XINT3 30
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#define IRQ_IOP32X_HPI 31
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#define NR_IRQS 32
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#endif // _IRQ_H_
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#endif
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/*
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* linux/include/asm-arm/arch-iop32x/memory.h
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* include/asm-arm/arch-iop32x/memory.h
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#ifndef __MEMORY_H
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#define __MEMORY_H
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#include <asm/hardware.h>
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* bus_to_virt: Used to convert an address for DMA operations
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* to an address that the kernel can use.
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*/
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#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
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#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
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@ -1,7 +1,7 @@
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/*
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* linux/include/asm-arm/arch-iop32x/system.h
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* include/asm-arm/arch-iop32x/system.h
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*
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* Copyright (C) 2001 MontaVista Software, Inc.
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* Copyright (C) 2001 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -13,17 +13,10 @@ static inline void arch_idle(void)
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cpu_do_idle();
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}
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static inline void arch_reset(char mode)
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{
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*IOP3XX_PCSR = 0x30;
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*IOP3XX_PCSR = 0x30;
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if ( 1 && mode == 's') {
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/* Jump into ROM at address 0 */
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cpu_reset(0);
|
||||
} else {
|
||||
/* No on-chip reset capability */
|
||||
cpu_reset(0);
|
||||
}
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop32x/timex.h
|
||||
* include/asm-arm/arch-iop32x/timex.h
|
||||
*
|
||||
* IOP3xx architecture timex specifications
|
||||
* IOP32x architecture timex specifications
|
||||
*/
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop32x/uncompress.h
|
||||
* include/asm-arm/arch-iop32x/uncompress.h
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
|
@ -8,13 +9,13 @@
|
|||
|
||||
static volatile u8 *uart_base;
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
|
||||
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
|
||||
|
||||
static inline void putc(char c)
|
||||
{
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
*uart_base = c;
|
||||
uart_base[UART_TX] = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
|
|
|
|||
|
|
@ -1,16 +1,5 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop32x/vmalloc.h
|
||||
* include/asm-arm/arch-iop32x/vmalloc.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* Just any arbitrary offset to the start of the vmalloc VM area: the
|
||||
* current 8MB value just means that there will be a 8MB "hole" after the
|
||||
* physical memory until the kernel virtual memory starts. That means that
|
||||
* any out-of-bounds memory accesses will hopefully be caught.
|
||||
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
|
||||
* area for the same reason. ;)
|
||||
*/
|
||||
//#define VMALLOC_END (0xe8000000)
|
||||
/* increase usable physical RAM to ~992M per RMK */
|
||||
#define VMALLOC_END (0xfe000000)
|
||||
|
||||
#define VMALLOC_END 0xfe000000
|
||||
|
|
|
|||
|
|
@ -1,17 +1,17 @@
|
|||
/* linux/include/asm-arm/arch-iop33x/debug-macro.S
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
*/
|
||||
|
||||
.macro addruart,rx
|
||||
.macro addruart, rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ mmu enabled?
|
||||
moveq \rx, #0xff000000 @ physical
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/dma.h
|
||||
* include/asm-arm/arch-iop33x/dma.h
|
||||
*
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@
|
|||
*
|
||||
* Low-level IRQ helper macros for IOP33x-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <asm/arch/irqs.h>
|
||||
#include <asm/arch/iop33x.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \base, =IOP3XX_REG_ADDR(0x07C8)
|
||||
ldr \irqstat, [\base] @ Read IINTVEC
|
||||
cmp \irqstat, #0
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/hardware.h
|
||||
* include/asm-arm/arch-iop33x/hardware.h
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#ifndef __HARDWARE_H
|
||||
#define __HARDWARE_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
|
|
@ -15,14 +16,15 @@
|
|||
* The PCI IO space is located at virtual 0xfe000000 from physical
|
||||
* 0x90000000. The PCI BARs must be programmed with physical addresses,
|
||||
* but when we read them, we convert them to virtual addresses. See
|
||||
* arch/arm/mach-iop33x/pci.c
|
||||
* arch/arm/mach-iop3xx/iop3xx-pci.c
|
||||
*/
|
||||
|
||||
#define pcibios_assign_all_busses() 1
|
||||
#define pcibios_assign_all_busses() 1
|
||||
#define PCIBIOS_MIN_IO 0x00000000
|
||||
#define PCIBIOS_MIN_MEM 0x00000000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void iop33x_init_irq(void);
|
||||
|
||||
extern struct platform_device iop33x_uart0_device;
|
||||
extern struct platform_device iop33x_uart1_device;
|
||||
#endif
|
||||
|
|
@ -32,7 +34,7 @@ extern struct platform_device iop33x_uart1_device;
|
|||
* Generic chipset bits
|
||||
*
|
||||
*/
|
||||
#include "iop331.h"
|
||||
#include "iop33x.h"
|
||||
|
||||
/*
|
||||
* Board specific bits
|
||||
|
|
@ -40,4 +42,5 @@ extern struct platform_device iop33x_uart1_device;
|
|||
#include "iq80331.h"
|
||||
#include "iq80332.h"
|
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,21 +1,21 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/io.h
|
||||
* include/asm-arm/arch-iop33x/io.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
#ifndef __IO_H
|
||||
#define __IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
#define __io(p) ((void __iomem *)(p))
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,110 +0,0 @@
|
|||
/*
|
||||
* linux/include/asm/arch-iop33x/iop331.h
|
||||
*
|
||||
* Intel IOP331 Chip definitions
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright (C) 2003, 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _IOP331_HW_H_
|
||||
#define _IOP331_HW_H_
|
||||
|
||||
|
||||
/*
|
||||
* This is needed for mixed drivers that need to work on all
|
||||
* IOP3xx variants but behave slightly differently on each.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define iop_is_331() 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IOP331 chipset registers
|
||||
*/
|
||||
#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
|
||||
#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
|
||||
#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
|
||||
|
||||
/* Reserved 0x00000000 through 0x000000FF */
|
||||
|
||||
/* Address Translation Unit 0x00000100 through 0x000001FF */
|
||||
|
||||
/* Messaging Unit 0x00000300 through 0x000003FF */
|
||||
|
||||
/* DMA Controller 0x00000400 through 0x000004FF */
|
||||
|
||||
/* Memory controller 0x00000500 through 0x0005FF */
|
||||
|
||||
/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
|
||||
|
||||
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
|
||||
/* Internal arbitration unit 0x00000780 through 0x0007BF */
|
||||
|
||||
/* Interrupt Controller */
|
||||
#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
|
||||
#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
|
||||
#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
|
||||
#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
|
||||
#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
|
||||
#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
|
||||
#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
|
||||
#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
|
||||
#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
|
||||
#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
|
||||
#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
|
||||
#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
|
||||
#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
|
||||
#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
|
||||
#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
|
||||
#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
|
||||
|
||||
|
||||
/* Application accelerator unit 0x00000800 - 0x000008FF */
|
||||
|
||||
#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
|
||||
#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
|
||||
/* SSP serial port unit 0x00001600 - 0x0000167F */
|
||||
|
||||
/* I2C bus interface unit 0x00001680 - 0x000016FF */
|
||||
|
||||
/* 0x00001700 through 0x0000172C UART 0 */
|
||||
|
||||
/* Reserved 0x00001730 through 0x0000173F */
|
||||
|
||||
/* 0x00001740 through 0x0000176C UART 1 */
|
||||
|
||||
#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
|
||||
#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
|
||||
#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
|
||||
#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
|
||||
|
||||
/* Reserved 0x00001770 through 0x0000177F */
|
||||
|
||||
/* General Purpose I/O Registers */
|
||||
#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
|
||||
#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
|
||||
#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
|
||||
|
||||
/* Reserved 0x0000178c through 0x000019ff */
|
||||
|
||||
/*
|
||||
* Peripherals that are shared between the iop32x and iop33x but
|
||||
* located at different addresses.
|
||||
*/
|
||||
#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
|
||||
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
|
||||
|
||||
#include <asm/hardware/iop3xx.h>
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iop331_init_irq(void);
|
||||
extern void iop331_time_init(void);
|
||||
#endif
|
||||
|
||||
#endif // _IOP331_HW_H_
|
||||
33
include/asm-arm/arch-iop33x/iop33x.h
Normal file
33
include/asm-arm/arch-iop33x/iop33x.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* include/asm-arm/arch-iop33x/iop33x.h
|
||||
*
|
||||
* Intel IOP33X Chip definitions
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright (C) 2003, 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IOP33X_H
|
||||
#define __IOP33X_H
|
||||
|
||||
/*
|
||||
* Peripherals that are shared between the iop32x and iop33x but
|
||||
* located at different addresses.
|
||||
*/
|
||||
#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
|
||||
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
|
||||
|
||||
#include <asm/hardware/iop3xx.h>
|
||||
|
||||
/* UARTs */
|
||||
#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
|
||||
#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
|
||||
#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
|
||||
#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,11 +1,11 @@
|
|||
/*
|
||||
* linux/include/asm/arch-iop33x/iq80331.h
|
||||
* include/asm-arm/arch-iop33x/iq80331.h
|
||||
*
|
||||
* Intel IQ80331 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ80331_H_
|
||||
#define _IQ80331_H_
|
||||
#ifndef __IQ80331_H
|
||||
#define __IQ80331_H
|
||||
|
||||
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
|
||||
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
|
||||
|
|
@ -13,4 +13,4 @@
|
|||
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
|
||||
|
||||
|
||||
#endif // _IQ80331_H_
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/*
|
||||
* linux/include/asm/arch-iop33x/iq80332.h
|
||||
* include/asm-arm/arch-iop33x/iq80332.h
|
||||
*
|
||||
* Intel IQ80332 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ80332_H_
|
||||
#define _IQ80332_H_
|
||||
#ifndef __IQ80332_H
|
||||
#define __IQ80332_H
|
||||
|
||||
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
|
||||
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
|
||||
|
|
@ -13,4 +13,4 @@
|
|||
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
|
||||
|
||||
|
||||
#endif // _IQ80332_H_
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/irqs.h
|
||||
* include/asm-arm/arch-iop33x/irqs.h
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright: (C) 2003 Intel Corp.
|
||||
|
|
@ -7,54 +7,54 @@
|
|||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef _IRQS_H_
|
||||
#define _IRQS_H_
|
||||
|
||||
#ifndef __IRQS_H
|
||||
#define __IRQS_H
|
||||
|
||||
/*
|
||||
* IOP80331 chipset interrupts
|
||||
*/
|
||||
#define IRQ_IOP331_DMA0_EOT 0
|
||||
#define IRQ_IOP331_DMA0_EOC 1
|
||||
#define IRQ_IOP331_DMA1_EOT 2
|
||||
#define IRQ_IOP331_DMA1_EOC 3
|
||||
#define IRQ_IOP331_AA_EOT 6
|
||||
#define IRQ_IOP331_AA_EOC 7
|
||||
#define IRQ_IOP331_TIMER0 8
|
||||
#define IRQ_IOP331_TIMER1 9
|
||||
#define IRQ_IOP331_I2C_0 10
|
||||
#define IRQ_IOP331_I2C_1 11
|
||||
#define IRQ_IOP331_MSG 12
|
||||
#define IRQ_IOP331_MSGIBQ 13
|
||||
#define IRQ_IOP331_ATU_BIST 14
|
||||
#define IRQ_IOP331_PERFMON 15
|
||||
#define IRQ_IOP331_CORE_PMU 16
|
||||
#define IRQ_IOP331_XINT0 24
|
||||
#define IRQ_IOP331_XINT1 25
|
||||
#define IRQ_IOP331_XINT2 26
|
||||
#define IRQ_IOP331_XINT3 27
|
||||
#define IRQ_IOP331_XINT8 32
|
||||
#define IRQ_IOP331_XINT9 33
|
||||
#define IRQ_IOP331_XINT10 34
|
||||
#define IRQ_IOP331_XINT11 35
|
||||
#define IRQ_IOP331_XINT12 36
|
||||
#define IRQ_IOP331_XINT13 37
|
||||
#define IRQ_IOP331_XINT14 38
|
||||
#define IRQ_IOP331_XINT15 39
|
||||
#define IRQ_IOP331_UART0 51
|
||||
#define IRQ_IOP331_UART1 52
|
||||
#define IRQ_IOP331_PBIE 53
|
||||
#define IRQ_IOP331_ATU_CRW 54
|
||||
#define IRQ_IOP331_ATU_ERR 55
|
||||
#define IRQ_IOP331_MCU_ERR 56
|
||||
#define IRQ_IOP331_DMA0_ERR 57
|
||||
#define IRQ_IOP331_DMA1_ERR 58
|
||||
#define IRQ_IOP331_AA_ERR 60
|
||||
#define IRQ_IOP331_MSG_ERR 62
|
||||
#define IRQ_IOP331_HPI 63
|
||||
#define IRQ_IOP33X_DMA0_EOT 0
|
||||
#define IRQ_IOP33X_DMA0_EOC 1
|
||||
#define IRQ_IOP33X_DMA1_EOT 2
|
||||
#define IRQ_IOP33X_DMA1_EOC 3
|
||||
#define IRQ_IOP33X_AA_EOT 6
|
||||
#define IRQ_IOP33X_AA_EOC 7
|
||||
#define IRQ_IOP33X_TIMER0 8
|
||||
#define IRQ_IOP33X_TIMER1 9
|
||||
#define IRQ_IOP33X_I2C_0 10
|
||||
#define IRQ_IOP33X_I2C_1 11
|
||||
#define IRQ_IOP33X_MSG 12
|
||||
#define IRQ_IOP33X_MSGIBQ 13
|
||||
#define IRQ_IOP33X_ATU_BIST 14
|
||||
#define IRQ_IOP33X_PERFMON 15
|
||||
#define IRQ_IOP33X_CORE_PMU 16
|
||||
#define IRQ_IOP33X_XINT0 24
|
||||
#define IRQ_IOP33X_XINT1 25
|
||||
#define IRQ_IOP33X_XINT2 26
|
||||
#define IRQ_IOP33X_XINT3 27
|
||||
#define IRQ_IOP33X_XINT8 32
|
||||
#define IRQ_IOP33X_XINT9 33
|
||||
#define IRQ_IOP33X_XINT10 34
|
||||
#define IRQ_IOP33X_XINT11 35
|
||||
#define IRQ_IOP33X_XINT12 36
|
||||
#define IRQ_IOP33X_XINT13 37
|
||||
#define IRQ_IOP33X_XINT14 38
|
||||
#define IRQ_IOP33X_XINT15 39
|
||||
#define IRQ_IOP33X_UART0 51
|
||||
#define IRQ_IOP33X_UART1 52
|
||||
#define IRQ_IOP33X_PBIE 53
|
||||
#define IRQ_IOP33X_ATU_CRW 54
|
||||
#define IRQ_IOP33X_ATU_ERR 55
|
||||
#define IRQ_IOP33X_MCU_ERR 56
|
||||
#define IRQ_IOP33X_DMA0_ERR 57
|
||||
#define IRQ_IOP33X_DMA1_ERR 58
|
||||
#define IRQ_IOP33X_AA_ERR 60
|
||||
#define IRQ_IOP33X_MSG_ERR 62
|
||||
#define IRQ_IOP33X_HPI 63
|
||||
|
||||
#define NR_IRQS 64
|
||||
|
||||
|
||||
#endif // _IRQ_H_
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/memory.h
|
||||
* include/asm-arm/arch-iop33x/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
#ifndef __MEMORY_H
|
||||
#define __MEMORY_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/system.h
|
||||
* include/asm-arm/arch-iop33x/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -13,17 +13,10 @@ static inline void arch_idle(void)
|
|||
cpu_do_idle();
|
||||
}
|
||||
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
*IOP3XX_PCSR = 0x30;
|
||||
*IOP3XX_PCSR = 0x30;
|
||||
|
||||
if ( 1 && mode == 's') {
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
} else {
|
||||
/* No on-chip reset capability */
|
||||
cpu_reset(0);
|
||||
}
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/timex.h
|
||||
* include/asm-arm/arch-iop33x/timex.h
|
||||
*
|
||||
* IOP3xx architecture timex specifications
|
||||
*/
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/uncompress.h
|
||||
* include/asm-arm/arch-iop33x/uncompress.h
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
|
|
@ -8,13 +9,13 @@
|
|||
|
||||
static volatile u32 *uart_base;
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
|
||||
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
|
||||
|
||||
static inline void putc(char c)
|
||||
{
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
*uart_base = c;
|
||||
uart_base[UART_TX] = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
|
|
@ -24,7 +25,7 @@ static inline void flush(void)
|
|||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
if (machine_is_iq80331() || machine_is_iq80332())
|
||||
uart_base = (volatile u32 *)IOP331_UART0_PHYS;
|
||||
uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
|
||||
else
|
||||
uart_base = (volatile u32 *)0xfe800000;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,16 +1,5 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-iop33x/vmalloc.h
|
||||
* include/asm-arm/arch-iop33x/vmalloc.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* Just any arbitrary offset to the start of the vmalloc VM area: the
|
||||
* current 8MB value just means that there will be a 8MB "hole" after the
|
||||
* physical memory until the kernel virtual memory starts. That means that
|
||||
* any out-of-bounds memory accesses will hopefully be caught.
|
||||
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
|
||||
* area for the same reason. ;)
|
||||
*/
|
||||
//#define VMALLOC_END (0xe8000000)
|
||||
/* increase usable physical RAM to ~992M per RMK */
|
||||
#define VMALLOC_END (0xfe000000)
|
||||
|
||||
#define VMALLOC_END 0xfe000000
|
||||
|
|
|
|||
Loading…
Reference in a new issue