From c86af5a8515334bb404f0ecc0cee97c9424c6c46 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Wed, 19 Aug 2020 16:40:50 +0530 Subject: [PATCH] msm: kgsl: Enable HWCG after a6xx register configurations For A6xx GPU enable hardware clock gating after register configuration to avoid register access issue due to hardware internal clock gating. Change-Id: If55632ccf9171a7093bb1e925e4fcdb88066417c Signed-off-by: Hareesh Gundu --- drivers/gpu/msm/adreno_a6xx.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 5afbe538ae74..601131040f1a 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -423,9 +423,6 @@ void a6xx_start(struct adreno_device *adreno_dev) unsigned int rgb565_predicator = 0; static bool patch_reglist; - /* enable hardware clockgating */ - a6xx_hwcg_set(adreno_dev, true); - /* Enable 64 bit addressing */ kgsl_regwrite(device, A6XX_CP_ADDR_MODE_CNTL, 0x1); kgsl_regwrite(device, A6XX_VSC_ADDR_MODE_CNTL, 0x1); @@ -657,6 +654,12 @@ void a6xx_start(struct adreno_device *adreno_dev) a6xx_set_secvid(device); + /* + * Enable hardware clock gating here to prevent any register access + * issue due to internal clock gating. + */ + a6xx_hwcg_set(adreno_dev, true); + /* * All registers must be written before this point so that we don't * miss any register programming when we patch the power up register