From 9343c6741da005ed490d71e93f82309460952bc0 Mon Sep 17 00:00:00 2001
From: Veera Vegivada <vvegivad@qti.qualcomm.com>
Date: Sun, 25 Apr 2021 00:43:45 +0530
Subject: [PATCH] dt-bindings: clock: Add support for QCS404 clock controllers

Update the GCC and DEBUGCC bindings for QCS404 device.

Change-Id: I3f327b4befb56282a767c1dd6e1e8b1d1d4b773e
---
 bindings/clock/qcom,cmn-blk-pll.txt | 26 ++++++++++++++++++++++++++
 bindings/clock/qcom,debugcc.txt     |  1 +
 bindings/clock/qcom,gcc.txt         |  1 +
 3 files changed, 28 insertions(+)
 create mode 100644 bindings/clock/qcom,cmn-blk-pll.txt

diff --git a/bindings/clock/qcom,cmn-blk-pll.txt b/bindings/clock/qcom,cmn-blk-pll.txt
new file mode 100644
index 000000000000..ae6ae72bad04
--- /dev/null
+++ b/bindings/clock/qcom,cmn-blk-pll.txt
@@ -0,0 +1,26 @@
+Qualcomm Technologies, Inc. Common Block PLL Controller Binding
+---------------------------------------------------------------
+
+Required properties :
+- compatible : shall contain only the following:
+			"qcom,cmn_blk_pll"
+
+- reg : shall contain base register location and size.
+- reg-names : "cmn_blk".
+- clock-names : Shall contain "misc_reset", "ahb_clk", "aon_clk".
+- clocks : phandle + clock reference to misc_reset, ahb and aon clock.
+- #clock-cells : shall contain 1.
+
+Example :
+	clock_cmn_blk_pll@2f780 {
+		compatible = "qcom,cmn_blk_pll";
+		reg = <0x2f780 0x4>;
+		reg-names = "cmn_blk";
+		clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>,
+			<&clock_gcc GCC_BIAS_PLL_AHB_CLK>,
+			<&clock_gcc GCC_BIAS_PLL_AON_CLK>;
+		clock-names = "misc_reset_clk", "ahb_clk", "aon_clk";
+		resets = <&clock_gcc GCC_BIAS_PLL_BCR>;
+		reset-names = "cmn_blk_pll_reset";
+		#clock-cells = <1>;
+	};
diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index 2b46f69dacf9..baa2b6a2f7fb 100644
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -17,6 +17,7 @@ Required properties :
 			"qcom,direwolf-debugcc"
 			"qcom,blair-debugcc"
 			"qcom,scuba-debugcc"
+			"qcom,qcs404-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 9f64f68d09a0..0db8e2851742 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -41,6 +41,7 @@ Required properties :
 			"qcom,direwolf-gcc"
 			"qcom,blair-gcc"
 			"qcom,scuba-gcc"
+			"qcom,qcs404-gcc-mdss"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.