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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (91 commits) [MTD] [NAND] Blackfin on-chip NAND Flash Controller driver [MTD] [NOR] fix ctrl-alt-del can't reboot for intel flash bug [MTD] [NAND] Fix compiler warning in Alauda driver [JFFS2] Remove stray debugging printk [JFFS2] Handle dirents on the flash with embedded zero bytes in names. [JFFS2] Check for creation of dirents with embedded zero bytes in name. [JFFS2] Don't count all 'very dirty' blocks except in debug mode [JFFS2] Check whether garbage-collection actually obsoleted its victim. [JFFS2] Relax threshold for triggering GC due to dirty blocks. [MTD] [OneNAND] Fix typo related with recent commit [JFFS2] Trigger garbage collection when very_dirty_list size becomes excessive [MTD] [NAND] Avoid deadlock in erase callback; release chip lock first. [MTD] [NAND] Resume method for CAFÉ NAND controller [MTD] [NAND] Fix PCI ident table for CAFÉ NAND controller. [MTD] [NAND] s3c2410: fix arch moves [MTD] [OneNAND] fix numerous races [MTD] map driver for NOR flash on the Intel Vermilion Range chipset [JFFS2] Fix unpoint length [MTD] fix CFI point method for discontiguous maps [MTD] MAPS: Merge Lubbock and Mainstone drivers into common PXA2xx driver ...
This commit is contained in:
commit
c8c55bcb43
91 changed files with 4671 additions and 2226 deletions
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@ -46,6 +46,7 @@
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#define JFFS2_COMPR_COPY 0x04
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#define JFFS2_COMPR_DYNRUBIN 0x05
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#define JFFS2_COMPR_ZLIB 0x06
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#define JFFS2_COMPR_LZO 0x07
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/* Compatibility flags. */
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#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */
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#define JFFS2_NODE_ACCURATE 0x2000
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@ -57,6 +57,15 @@
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#define cfi_interleave_is_8(cfi) (0)
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#endif
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#ifndef cfi_interleave
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#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
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static inline int cfi_interleave(void *cfi)
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{
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BUG();
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return 0;
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}
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#endif
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static inline int cfi_interleave_supported(int i)
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{
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switch (i) {
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@ -40,6 +40,7 @@ typedef enum {
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FL_POINT,
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FL_XIP_WHILE_ERASING,
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FL_XIP_WHILE_WRITING,
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FL_SHUTDOWN,
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FL_UNKNOWN
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} flstate_t;
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@ -125,7 +125,15 @@
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#endif
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#ifndef map_bankwidth
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#error "No bus width supported. What's the point?"
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#warning "No CONFIG_MTD_MAP_BANK_WIDTH_xx selected. No NOR chip support can work"
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static inline int map_bankwidth(void *map)
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{
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BUG();
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return 0;
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}
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#define map_bankwidth_is_large(map) (0)
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#define map_words(map) (0)
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#define MAX_MAP_BANKWIDTH 1
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#endif
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static inline int map_bankwidth_supported(int w)
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@ -133,6 +133,13 @@ struct mtd_info {
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int numeraseregions;
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struct mtd_erase_region_info *eraseregions;
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/*
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* Erase is an asynchronous operation. Device drivers are supposed
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* to call instr->callback() whenever the operation completes, even
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* if it completes with a failure.
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* Callers are supposed to pass a callback function and wait for it
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* to be called before writing to the block.
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*/
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int (*erase) (struct mtd_info *mtd, struct erase_info *instr);
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/* This stuff for eXecute-In-Place */
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@ -432,6 +432,7 @@ struct nand_chip {
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#define NAND_MFR_STMICRO 0x20
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#define NAND_MFR_HYNIX 0xad
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#define NAND_MFR_MICRON 0x2c
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#define NAND_MFR_AMD 0x01
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/**
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* struct nand_flash_dev - NAND Flash Device ID Structure
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@ -60,6 +60,7 @@ struct onenand_bufferram {
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* @erase_shift: [INTERN] number of address bits in a block
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* @page_shift: [INTERN] number of address bits in a page
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* @page_mask: [INTERN] a page per block mask
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* @writesize: [INTERN] a real page size
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* @bufferram_index: [INTERN] BufferRAM index
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* @bufferram: [INTERN] BufferRAM info
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* @readw: [REPLACEABLE] hardware specific function for read short
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@ -100,6 +101,7 @@ struct onenand_chip {
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unsigned int erase_shift;
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unsigned int page_shift;
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unsigned int page_mask;
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unsigned int writesize;
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unsigned int bufferram_index;
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struct onenand_bufferram bufferram[MAX_BUFFERRAM];
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@ -140,6 +142,8 @@ struct onenand_chip {
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#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
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#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
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#define ONENAND_SET_PREV_BUFFERRAM(this) (this->bufferram_index ^= 1)
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#define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0)
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#define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1)
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#define ONENAND_GET_SYS_CFG1(this) \
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(this->read_word(this->base + ONENAND_REG_SYS_CFG1))
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@ -149,6 +153,13 @@ struct onenand_chip {
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#define ONENAND_IS_DDP(this) \
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(this->device_id & ONENAND_DEVICE_IS_DDP)
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#ifdef CONFIG_MTD_ONENAND_2X_PROGRAM
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#define ONENAND_IS_2PLANE(this) \
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(this->options & ONENAND_HAS_2PLANE)
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#else
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#define ONENAND_IS_2PLANE(this) (0)
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#endif
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/* Check byte access in OneNAND */
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#define ONENAND_CHECK_BYTE_ACCESS(addr) (addr & 0x1)
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@ -157,6 +168,7 @@ struct onenand_chip {
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*/
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#define ONENAND_HAS_CONT_LOCK (0x0001)
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#define ONENAND_HAS_UNLOCK_ALL (0x0002)
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#define ONENAND_HAS_2PLANE (0x0004)
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#define ONENAND_PAGEBUF_ALLOC (0x1000)
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#define ONENAND_OOBBUF_ALLOC (0x2000)
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@ -74,6 +74,8 @@
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#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
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#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
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#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
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#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
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/*
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* Version ID Register F002h (R)
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@ -111,6 +113,8 @@
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#define ONENAND_CMD_READOOB (0x13)
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#define ONENAND_CMD_PROG (0x80)
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#define ONENAND_CMD_PROGOOB (0x1A)
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#define ONENAND_CMD_2X_PROG (0x7D)
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#define ONENAND_CMD_2X_CACHE_PROG (0x7F)
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#define ONENAND_CMD_UNLOCK (0x23)
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#define ONENAND_CMD_LOCK (0x2A)
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#define ONENAND_CMD_LOCK_TIGHT (0x2C)
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