From c97537f9ec4311739aa319b01de77ef6835284aa Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 5 Jan 2021 20:10:48 +0530 Subject: [PATCH] ARM: dts: msm: Add device node for llcc node on SDMSHRIKE Add device node for last level cache controller on SDMSHRIKE target. Change-Id: I33ef1895e9228cf897942051eb1f7fd7596d79a1 --- bindings/arm/msm/qcom,llcc.txt | 1 + qcom/sdmshrike.dtsi | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index c7640f8bf122..6bddb3cbb70c 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,6 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" + or "qcom,sdmshrike-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index bbaed2bd035b..6191c8b4045b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -621,6 +621,13 @@ }; }; + cache-controller@9200000 { + compatible = "qcom,sdmshrike-llcc"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>;