From c9a7ad232a9ea6df4312d2ba8a702d3ae0d8d4bf Mon Sep 17 00:00:00 2001
From: "Tao,Zhang" <taozha@qti.qualcomm.com>
Date: Tue, 27 Oct 2020 11:15:45 +0800
Subject: [PATCH] ARM: dts: msm: Add cti trigger number to device tree for holi

Add cti trigger number to device tree for holi. Since some
platforms don't have swao cti, replace configuring cti trigger
number as hard code.

Change-Id: Ibb96b02f966c765f8744a278bb6b6f18da2edd4c
---
 qcom/holi-coresight.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi
index 95a7723749e2..817a8365d552 100644
--- a/qcom/holi-coresight.dtsi
+++ b/qcom/holi-coresight.dtsi
@@ -1959,6 +1959,9 @@
 		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
 		clock-names = "apb_pclk";
 		coresight-ctis = <&cti0 &cti6>;
+		cti-reset-trig-num = <5>;
+		cti-flush-trig-num = <1>;
+
 		in-ports {
 			port {
 				tmc_etf_in_funnel_merge: endpoint {
@@ -2039,6 +2042,8 @@
 		qcom,sw-usb;
 
 		coresight-ctis = <&cti0 &cti6>;
+		cti-reset-trig-num = <5>;
+		cti-flush-trig-num = <3>;
 		coresight-csr = <&csr>;
 		interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
 		interrupt-names = "byte-cntr-irq";