mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Pin control bulk changes for the v4.21 kernel cycle:
No core changes this time.
New drivers:
- NXP (ex Freescale) i.MX 8 QXP SoC driver.
- Mediatek MT6797 SoC driver.
- Mediatek MT7629 SoC driver.
- Actions Semiconductor S700 SoC driver.
- Renesas RZ/A2 SoC driver.
- Allwinner sunxi suniv F1C100 SoC driver.
- Qualcomm PMS405 PMIC driver.
- Microsemi Ocelot Jaguar2 SoC driver.
Improvements:
- Some RT improvements (using raw spinlocks where appropriate).
- A lot of new pin sets on the Renesas PFC pin controllers.
- GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
chips, and Xway.
- Major modernization of the Intel pin control drivers.
- STM32 pin control driver will now synchronize usage of pins
with another CPU using a hardware spinlock.
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Merge tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"We have no core changes but lots of incremental development in drivers
all over the place: Renesas, NXP, Mediatek and Actions Semiconductor
keep churning out new SoCs.
I have some subtree maintainers for Renesas and Intel helping out to
keep down the load, it's been working smoothly (Samsung also have a
subtree but it was not used this cycle.)
New drivers:
- NXP (ex Freescale) i.MX 8 QXP SoC driver.
- Mediatek MT6797 SoC driver.
- Mediatek MT7629 SoC driver.
- Actions Semiconductor S700 SoC driver.
- Renesas RZ/A2 SoC driver.
- Allwinner sunxi suniv F1C100 SoC driver.
- Qualcomm PMS405 PMIC driver.
- Microsemi Ocelot Jaguar2 SoC driver.
Improvements:
- Some RT improvements (using raw spinlocks where appropriate).
- A lot of new pin sets on the Renesas PFC pin controllers.
- GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
chips, and Xway.
- Major modernization of the Intel pin control drivers.
- STM32 pin control driver will now synchronize usage of pins with
another CPU using a hardware spinlock"
* tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits)
dt-bindings: arm: fsl-scu: add imx8qm pinctrl support
pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ
pinctrl: imx-scu: Depend on IMX_SCU
pinctrl: ocelot: Add dependency on HAS_IOMEM
pinctrl: ocelot: add MSCC Jaguar2 support
pinctrl: bcm: ns: support updated DT binding as syscon subnode
dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
MAINTAINERS: merge at91 pinctrl entries
pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
pinctrl: uniphier: constify uniphier_pinctrl_socdata
pinctrl: mediatek: improve Kconfig dependencies
pinctrl: msm: mark PM functions as __maybe_unused
dt-bindings: pinctrl: sunxi: Add supply properties
pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
...
This commit is contained in:
Linus Torvalds
commit
c9bef4a651
117 changed files with 14485 additions and 1405 deletions
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@ -88,13 +88,16 @@ Pinctrl bindings based on SCU Message Protocol
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This binding uses the i.MX common pinctrl binding[3].
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Required properties:
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- compatible: Should be "fsl,imx8qxp-iomuxc".
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- compatible: Should be one of:
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"fsl,imx8qm-iomuxc",
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"fsl,imx8qxp-iomuxc".
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Required properties for Pinctrl sub nodes:
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- fsl,pins: Each entry consists of 3 integers which represents
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the mux and config setting for one pin. The first 2
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integers <pin_id mux_mode> are specified using a
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PIN_FUNC_ID macro, which can be found in
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<dt-bindings/pinctrl/pads-imx8qm.h>,
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<dt-bindings/pinctrl/pads-imx8qxp.h>.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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|
|
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@ -0,0 +1,170 @@
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Actions Semi S700 Pin Controller
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This binding describes the pin controller found in the S700 SoC.
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Required Properties:
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- compatible: Should be "actions,s700-pinctrl"
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- reg: Should contain the register base address and size of
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the pin controller.
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- clocks: phandle of the clock feeding the pin controller
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- gpio-controller: Marks the device node as a GPIO controller.
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- gpio-ranges: Specifies the mapping between gpio controller and
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pin-controller pins.
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- #gpio-cells: Should be two. The first cell is the gpio pin number
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and the second cell is used for optional parameters.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt. Shall be set to 2. The first cell
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defines the interrupt number, the second encodes
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the trigger flags described in
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bindings/interrupt-controller/interrupts.txt
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- interrupts: The interrupt outputs from the controller. There is one GPIO
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interrupt per GPIO bank. The number of interrupts listed depends
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on the number of GPIO banks on the SoC. The interrupts must be
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ordered by bank, starting with bank 0.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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Pinmux functions are available only for the pin groups while pinconf
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parameters are available for both pin groups and individual pins.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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Required Properties:
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- pins: An array of strings, each string containing the name of a pin.
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These pins are used for selecting the pull control and schmitt
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trigger parameters. The following are the list of pins
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available:
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eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
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eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
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eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
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i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
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pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
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ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
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lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
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lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
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lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
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lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
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dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
|
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sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
|
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sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
|
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uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
|
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uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
|
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i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
|
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csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
|
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sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
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dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
|
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dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
|
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dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
|
||||
dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
|
||||
|
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- groups: An array of strings, each string containing the name of a pin
|
||||
group. These pin groups are used for selecting the pinmux
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functions.
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rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
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rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
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rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
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i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
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i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
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ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
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dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
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lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
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dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
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uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
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sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
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uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
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i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
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pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
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nand_ceb2_mfp, nand_ceb3_mfp
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These pin groups are used for selecting the drive strength
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parameters.
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sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
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rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
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smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
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pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
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dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
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uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
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sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
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- function: An array of strings, each string containing the name of the
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pinmux functions. These functions can only be selected by
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the corresponding pin groups. The following are the list of
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pinmux functions available:
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nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
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uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
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pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
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sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
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clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
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Optional Properties:
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- bias-pull-down: No arguments. The specified pins should be configured as
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pull down.
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- bias-pull-up: No arguments. The specified pins should be configured as
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pull up.
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- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
|
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pins
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- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
|
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pins
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- drive-strength: Integer. Selects the drive strength for the specified
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pins in mA.
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Valid values are:
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<2>
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<4>
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<8>
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<12>
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Example:
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s700-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 136>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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uart3-default: uart3-default {
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pinmux {
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groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
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function = "uart3";
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};
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pinconf {
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groups = "uart3_all_drv";
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drive-strength = <2>;
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};
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};
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};
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@ -29,6 +29,7 @@ Required properties:
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"allwinner,sun50i-h5-pinctrl"
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"allwinner,sun50i-h6-pinctrl"
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"allwinner,sun50i-h6-r-pinctrl"
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"allwinner,suniv-f1c100s-pinctrl"
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"nextthing,gr8-pinctrl"
|
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|
||||
- reg: Should contain the register physical address and length for the
|
||||
|
|
@ -43,6 +44,19 @@ Note: For backward compatibility reasons, the hosc and losc clocks are only
|
|||
required if you need to use the optional input-debounce property. Any new
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device tree should set them.
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|
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Each pin bank, depending on the SoC, can have an associated regulator:
|
||||
|
||||
- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
|
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- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
|
||||
- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
|
||||
- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
|
||||
- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
|
||||
- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
|
||||
- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
|
||||
- vcc-ph-supply: for the A31, A31s and A80 SoCs
|
||||
- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
|
||||
- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
|
||||
|
||||
Optional properties:
|
||||
- input-debounce: Array of debouncing periods in microseconds. One period per
|
||||
irq bank found in the controller. 0 if no setup required.
|
||||
|
|
|
|||
|
|
@ -7,13 +7,15 @@ configure controller correctly.
|
|||
|
||||
A list of pins varies across chipsets so few bindings are available.
|
||||
|
||||
Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
|
||||
noce.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
"brcm,bcm4708-pinmux"
|
||||
"brcm,bcm4709-pinmux"
|
||||
"brcm,bcm53012-pinmux"
|
||||
- reg: iomem address range of CRU (Central Resource Unit) pin registers
|
||||
- reg-names: "cru_gpio_control" - the only needed & supported reg right now
|
||||
- offset: offset of pin registers in the CRU block
|
||||
|
||||
Functions and their groups available for all chipsets:
|
||||
- "spi": "spi_grp"
|
||||
|
|
@ -37,16 +39,12 @@ Example:
|
|||
#size-cells = <1>;
|
||||
|
||||
cru@100 {
|
||||
compatible = "simple-bus";
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x100 0x1a4>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pin-controller@1c0 {
|
||||
pinctrl {
|
||||
compatible = "brcm,bcm4708-pinmux";
|
||||
reg = <0x1c0 0x24>;
|
||||
reg-names = "cru_gpio_control";
|
||||
offset = <0xc0>;
|
||||
|
||||
spi-pins {
|
||||
function = "spi";
|
||||
|
|
|
|||
|
|
@ -7,55 +7,47 @@ Note:
|
|||
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
|
||||
supports generic pin config.
|
||||
|
||||
Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
|
||||
binding.
|
||||
|
||||
=== Pin Controller Node ===
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx7ulp-iomuxc1"
|
||||
- reg: Should contain the base physical address and size of the iomuxc
|
||||
registers.
|
||||
- compatible: "fsl,imx7ulp-iomuxc1".
|
||||
- fsl,pins: Each entry consists of 5 integers which represents the mux
|
||||
and config setting for one pin. The first 4 integers
|
||||
<mux_conf_reg input_reg mux_mode input_val> are specified
|
||||
using a PIN_FUNC_ID macro, which can be found in
|
||||
imx7ulp-pinfunc.h in the device tree source folder.
|
||||
The last integer CONFIG is the pad setting value like
|
||||
pull-up on this pin.
|
||||
|
||||
=== Pin Configuration Node ===
|
||||
- pinmux: One integers array, represents a group of pins mux setting.
|
||||
The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
|
||||
a specific function.
|
||||
Please refer to i.MX7ULP Reference Manual for detailed
|
||||
CONFIG settings.
|
||||
|
||||
NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
|
||||
and config register as follows:
|
||||
<mux_conf_reg input_reg mux_mode input_val>
|
||||
|
||||
Refer to imx7ulp-pinfunc.h in in device tree source folder for all
|
||||
available imx7ulp PIN_FUNC_ID.
|
||||
|
||||
Optional Properties:
|
||||
- drive-strength Integer. Controls Drive Strength
|
||||
0: Standard
|
||||
1: Hi Driver
|
||||
- drive-push-pull Bool. Enable Pin Push-pull
|
||||
- drive-open-drain Bool. Enable Pin Open-drian
|
||||
- slew-rate: Integer. Controls Slew Rate
|
||||
0: Standard
|
||||
1: Slow
|
||||
- bias-disable: Bool. Pull disabled
|
||||
- bias-pull-down: Bool. Pull down on pin
|
||||
- bias-pull-up: Bool. Pull up on pin
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_OBE (1 << 17)
|
||||
PAD_CTL_IBE (1 << 16)
|
||||
PAD_CTL_LK (1 << 16)
|
||||
PAD_CTL_DSE_HI (1 << 6)
|
||||
PAD_CTL_DSE_STD (0 << 6)
|
||||
PAD_CTL_ODE (1 << 5)
|
||||
PAD_CTL_PUSH_PULL (0 << 5)
|
||||
PAD_CTL_SRE_SLOW (1 << 2)
|
||||
PAD_CTL_SRE_STD (0 << 2)
|
||||
PAD_CTL_PE (1 << 0)
|
||||
|
||||
Examples:
|
||||
#include "imx7ulp-pinfunc.h"
|
||||
|
||||
/* Pin Controller Node */
|
||||
iomuxc1: iomuxc@40ac0000 {
|
||||
iomuxc1: pinctrl@40ac0000 {
|
||||
compatible = "fsl,imx7ulp-iomuxc1";
|
||||
reg = <0x40ac0000 0x1000>;
|
||||
|
||||
/* Pin Configuration Node */
|
||||
pinctrl_lpuart4: lpuart4grp {
|
||||
pinmux = <
|
||||
IMX7ULP_PAD_PTC3__LPUART4_RX
|
||||
IMX7ULP_PAD_PTC2__LPUART4_TX
|
||||
fsl,pins = <
|
||||
IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
|
||||
IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
|
||||
>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
|
|||
----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "mscc,ocelot-pinctrl"
|
||||
- compatible : Should be "mscc,ocelot-pinctrl" or
|
||||
"mscc,jaguar2-pinctrl"
|
||||
- reg : Address and length of the register set for the device
|
||||
- gpio-controller : Indicates this device is a GPIO controller
|
||||
- #gpio-cells : Must be 2.
|
||||
|
|
|
|||
83
Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt
Normal file
83
Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
* MediaTek MT6797 Pin Controller
|
||||
|
||||
The MediaTek's MT6797 Pin controller is used to control SoC pins.
|
||||
|
||||
Required properties:
|
||||
- compatible: Value should be one of the following.
|
||||
"mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
|
||||
- reg: Should contain address and size for gpio, iocfgl, iocfgb,
|
||||
iocfgr and iocfgt register bases.
|
||||
- reg-names: An array of strings describing the "reg" entries. Must
|
||||
contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
|
||||
- gpio-controller: Marks the device node as a gpio controller.
|
||||
- #gpio-cells: Should be two. The first cell is the gpio pin number
|
||||
and the second cell is used for optional parameters.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- interrupts : The interrupt outputs from the controller.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices.
|
||||
|
||||
Subnode format
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input schmitt.
|
||||
|
||||
node {
|
||||
pinmux = <PIN_NUMBER_PINMUX>;
|
||||
GENERIC_PINCONFIG;
|
||||
};
|
||||
|
||||
Required properties:
|
||||
- pinmux: Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
|
||||
|
||||
Optional properties:
|
||||
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
|
||||
bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
|
||||
input-schmitt-disable, output-enable output-low, output-high,
|
||||
drive-strength, and slew-rate are valid.
|
||||
|
||||
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
|
||||
'1' for slower slew rate respectively. Valid arguments for 'drive-strength'
|
||||
is limited, such as 2, 4, 8, 12, or 16 in mA.
|
||||
|
||||
Some optional vendor properties as defined are valid to specify in a
|
||||
pinconf subnode:
|
||||
- mediatek,tdsel: An integer describing the steps for output level shifter
|
||||
duty cycle when asserted (high pulse width adjustment). Valid arguments
|
||||
are from 0 to 15.
|
||||
- mediatek,rdsel: An integer describing the steps for input level shifter
|
||||
duty cycle when asserted (high pulse width adjustment). Valid arguments
|
||||
are from 0 to 63.
|
||||
- mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
|
||||
or 3 for the advanced pull-up resistors.
|
||||
- mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
|
||||
or 3 for the advanced pull-down resistors.
|
||||
|
||||
Examples:
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt6797-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>,
|
||||
<0 0x10002000 0 0x400>,
|
||||
<0 0x10002400 0 0x400>,
|
||||
<0 0x10002800 0 0x400>,
|
||||
<0 0x10002C00 0 0x400>;
|
||||
reg-names = "gpio", "iocfgl", "iocfgb",
|
||||
"iocfgr", "iocfgt";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
uart1_pins_a: uart1 {
|
||||
pins1 {
|
||||
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
|
||||
<MT6797_GPIO233__FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3,6 +3,7 @@
|
|||
Required properties for the root node:
|
||||
- compatible: Should be one of the following
|
||||
"mediatek,mt7622-pinctrl" for MT7622 SoC
|
||||
"mediatek,mt7629-pinctrl" for MT7629 SoC
|
||||
- reg: offset and length of the pinctrl space
|
||||
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
|
|
@ -324,6 +325,136 @@ group.
|
|||
"uart4_2_rts_cts" "uart" 95, 96
|
||||
"watchdog" "watchdog" 78
|
||||
|
||||
|
||||
== Valid values for pins, function and groups on MT7629 ==
|
||||
|
||||
Pin #: Valid values for pins
|
||||
-----------------------------
|
||||
PIN 0: "TOP_5G_CLK"
|
||||
PIN 1: "TOP_5G_DATA"
|
||||
PIN 2: "WF0_5G_HB0"
|
||||
PIN 3: "WF0_5G_HB1"
|
||||
PIN 4: "WF0_5G_HB2"
|
||||
PIN 5: "WF0_5G_HB3"
|
||||
PIN 6: "WF0_5G_HB4"
|
||||
PIN 7: "WF0_5G_HB5"
|
||||
PIN 8: "WF0_5G_HB6"
|
||||
PIN 9: "XO_REQ"
|
||||
PIN 10: "TOP_RST_N"
|
||||
PIN 11: "SYS_WATCHDOG"
|
||||
PIN 12: "EPHY_LED0_N_JTDO"
|
||||
PIN 13: "EPHY_LED1_N_JTDI"
|
||||
PIN 14: "EPHY_LED2_N_JTMS"
|
||||
PIN 15: "EPHY_LED3_N_JTCLK"
|
||||
PIN 16: "EPHY_LED4_N_JTRST_N"
|
||||
PIN 17: "WF2G_LED_N"
|
||||
PIN 18: "WF5G_LED_N"
|
||||
PIN 19: "I2C_SDA"
|
||||
PIN 20: "I2C_SCL"
|
||||
PIN 21: "GPIO_9"
|
||||
PIN 22: "GPIO_10"
|
||||
PIN 23: "GPIO_11"
|
||||
PIN 24: "GPIO_12"
|
||||
PIN 25: "UART1_TXD"
|
||||
PIN 26: "UART1_RXD"
|
||||
PIN 27: "UART1_CTS"
|
||||
PIN 28: "UART1_RTS"
|
||||
PIN 29: "UART2_TXD"
|
||||
PIN 30: "UART2_RXD"
|
||||
PIN 31: "UART2_CTS"
|
||||
PIN 32: "UART2_RTS"
|
||||
PIN 33: "MDI_TP_P1"
|
||||
PIN 34: "MDI_TN_P1"
|
||||
PIN 35: "MDI_RP_P1"
|
||||
PIN 36: "MDI_RN_P1"
|
||||
PIN 37: "MDI_RP_P2"
|
||||
PIN 38: "MDI_RN_P2"
|
||||
PIN 39: "MDI_TP_P2"
|
||||
PIN 40: "MDI_TN_P2"
|
||||
PIN 41: "MDI_TP_P3"
|
||||
PIN 42: "MDI_TN_P3"
|
||||
PIN 43: "MDI_RP_P3"
|
||||
PIN 44: "MDI_RN_P3"
|
||||
PIN 45: "MDI_RP_P4"
|
||||
PIN 46: "MDI_RN_P4"
|
||||
PIN 47: "MDI_TP_P4"
|
||||
PIN 48: "MDI_TN_P4"
|
||||
PIN 49: "SMI_MDC"
|
||||
PIN 50: "SMI_MDIO"
|
||||
PIN 51: "PCIE_PERESET_N"
|
||||
PIN 52: "PWM_0"
|
||||
PIN 53: "GPIO_0"
|
||||
PIN 54: "GPIO_1"
|
||||
PIN 55: "GPIO_2"
|
||||
PIN 56: "GPIO_3"
|
||||
PIN 57: "GPIO_4"
|
||||
PIN 58: "GPIO_5"
|
||||
PIN 59: "GPIO_6"
|
||||
PIN 60: "GPIO_7"
|
||||
PIN 61: "GPIO_8"
|
||||
PIN 62: "SPI_CLK"
|
||||
PIN 63: "SPI_CS"
|
||||
PIN 64: "SPI_MOSI"
|
||||
PIN 65: "SPI_MISO"
|
||||
PIN 66: "SPI_WP"
|
||||
PIN 67: "SPI_HOLD"
|
||||
PIN 68: "UART0_TXD"
|
||||
PIN 69: "UART0_RXD"
|
||||
PIN 70: "TOP_2G_CLK"
|
||||
PIN 71: "TOP_2G_DATA"
|
||||
PIN 72: "WF0_2G_HB0"
|
||||
PIN 73: "WF0_2G_HB1"
|
||||
PIN 74: "WF0_2G_HB2"
|
||||
PIN 75: "WF0_2G_HB3"
|
||||
PIN 76: "WF0_2G_HB4"
|
||||
PIN 77: "WF0_2G_HB5"
|
||||
PIN 78: "WF0_2G_HB6"
|
||||
|
||||
Valid values for function are:
|
||||
"eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart",
|
||||
"watchdog", "wifi"
|
||||
|
||||
Valid values for groups are:
|
||||
Valid value function pins (in pin#)
|
||||
----------------------------------------------------------------
|
||||
"mdc_mdio" "eth" 23, 24
|
||||
"i2c_0" "i2c" 19, 20
|
||||
"i2c_1" "i2c" 53, 54
|
||||
"ephy_leds" "led" 12, 13, 14, 15, 16,
|
||||
17, 18
|
||||
"ephy0_led" "led" 12
|
||||
"ephy1_led" "led" 13
|
||||
"ephy2_led" "led" 14
|
||||
"ephy3_led" "led" 15
|
||||
"ephy4_led" "led" 16
|
||||
"wf2g_led" "led" 17
|
||||
"wf5g_led" "led" 18
|
||||
"snfi" "flash" 62, 63, 64, 65, 66, 67
|
||||
"spi_nor" "flash" 62, 63, 64, 65, 66, 67
|
||||
"pcie_pereset" "pcie" 51
|
||||
"pcie_wake" "pcie" 55
|
||||
"pcie_clkreq" "pcie" 56
|
||||
"pwm_0" "pwm" 52
|
||||
"pwm_1" "pwm" 61
|
||||
"spi_0" "spi" 21, 22, 23, 24
|
||||
"spi_1" "spi" 62, 63, 64, 65
|
||||
"spi_wp" "spi" 66
|
||||
"spi_hold" "spi" 67
|
||||
"uart0_txd_rxd" "uart" 68, 69
|
||||
"uart1_0_txd_rxd" "uart" 25, 26
|
||||
"uart1_0_cts_rts" "uart" 27, 28
|
||||
"uart1_1_txd_rxd" "uart" 53, 54
|
||||
"uart1_1_cts_rts" "uart" 55, 56
|
||||
"uart2_0_txd_rxd" "uart" 29, 30
|
||||
"uart2_0_cts_rts" "uart" 31, 32
|
||||
"uart2_1_txd_rxd" "uart" 57, 58
|
||||
"uart2_1_cts_rts" "uart" 59, 60
|
||||
"watchdog" "watchdog" 11
|
||||
"wf0_2g" "wifi" 70, 71, 72, 73, 74,
|
||||
75, 76, 77, 78
|
||||
"wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,
|
||||
7, 8, 9, 10
|
||||
|
||||
Example:
|
||||
|
||||
pio: pinctrl@10211000 {
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ to specify in a pin configuration subnode:
|
|||
gpio1-gpio26 for pm8998
|
||||
gpio1-gpio22 for pma8084
|
||||
gpio1-gpio10 for pmi8994
|
||||
gpio1-gpio11 for pms405
|
||||
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
|
|
|
|||
|
|
@ -0,0 +1,87 @@
|
|||
Renesas RZ/A2 combined Pin and GPIO controller
|
||||
|
||||
The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
|
||||
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
||||
Each port features up to 8 pins, each of them configurable for GPIO
|
||||
function (port mode) or in alternate function mode.
|
||||
Up to 8 different alternate function modes exist for each single pin.
|
||||
|
||||
Pin controller node
|
||||
-------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be:
|
||||
- "renesas,r7s9210-pinctrl": for RZ/A2M
|
||||
- reg
|
||||
Address base and length of the memory area where the pin controller
|
||||
hardware is mapped to.
|
||||
- gpio-controller
|
||||
This pin controller also controls pins as GPIO
|
||||
- #gpio-cells
|
||||
Must be 2
|
||||
- gpio-ranges
|
||||
Expresses the total number of GPIO ports/pins in this SoC
|
||||
|
||||
Example: Pin controller node for RZ/A2M SoC (r7s9210)
|
||||
|
||||
pinctrl: pin-controller@fcffe000 {
|
||||
compatible = "renesas,r7s9210-pinctrl";
|
||||
reg = <0xfcffe000 0x1000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 176>;
|
||||
};
|
||||
|
||||
Sub-nodes
|
||||
---------
|
||||
|
||||
The child nodes of the pin controller designate pins to be used for
|
||||
specific peripheral functions or as GPIO.
|
||||
|
||||
- Pin multiplexing sub-nodes:
|
||||
A pin multiplexing sub-node describes how to configure a set of
|
||||
(or a single) pin in some desired alternate function mode.
|
||||
The values for the pinmux properties are a combination of port name, pin
|
||||
number and the desired function index. Use the RZA2_PINMUX macro located
|
||||
in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
|
||||
For assigning GPIO pins, use the macro RZA2_PIN also in r7s9210-pinctrl.h
|
||||
to express the desired port pin.
|
||||
|
||||
Required properties:
|
||||
- pinmux:
|
||||
integer array representing pin number and pin multiplexing configuration.
|
||||
When a pin has to be configured in alternate function mode, use this
|
||||
property to identify the pin by its global index, and provide its
|
||||
alternate function configuration number along with it.
|
||||
When multiple pins are required to be configured as part of the same
|
||||
alternate function they shall be specified as members of the same
|
||||
argument list of a single "pinmux" property.
|
||||
Helper macros to ease assembling the pin index from its position
|
||||
(port where it sits on and pin number) and alternate function identifier
|
||||
are provided by the pin controller header file at:
|
||||
<dt-bindings/pinctrl/r7s9210-pinctrl.h>
|
||||
Integers values in "pinmux" argument list are assembled as:
|
||||
((PORT * 8 + PIN) | MUX_FUNC << 16)
|
||||
|
||||
Example: Board specific pins configuration
|
||||
|
||||
&pinctrl {
|
||||
/* Serial Console */
|
||||
scif4_pins: serial4 {
|
||||
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
|
||||
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
|
||||
};
|
||||
};
|
||||
|
||||
Example: Assigning a GPIO:
|
||||
|
||||
leds {
|
||||
status = "okay";
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
/* P6_0 */
|
||||
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -56,6 +56,7 @@ Optional properties:
|
|||
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
|
||||
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
|
||||
used to select GPIOs as interrupts).
|
||||
- hwlocks: reference to a phandle of a hardware spinlock provider node.
|
||||
|
||||
Example 1:
|
||||
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
|
||||
|
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Reference in a new issue