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Pin control bulk changes for the v4.21 kernel cycle:

Browse source 
No core changes this time.
 
 New drivers:
 
 - NXP (ex Freescale) i.MX 8 QXP SoC driver.
 
 - Mediatek MT6797 SoC driver.
 
 - Mediatek MT7629 SoC driver.
 
 - Actions Semiconductor S700 SoC driver.
 
 - Renesas RZ/A2 SoC driver.
 
 - Allwinner sunxi suniv F1C100 SoC driver.
 
 - Qualcomm PMS405 PMIC driver.
 
 - Microsemi Ocelot Jaguar2 SoC driver.
 
 Improvements:
 
 - Some RT improvements (using raw spinlocks where appropriate).
 
 - A lot of new pin sets on the Renesas PFC pin controllers.
 
 - GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
   chips, and Xway.
 
 - Major modernization of the Intel pin control drivers.
 
 - STM32 pin control driver will now synchronize usage of pins
   with another CPU using a hardware spinlock.
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Merge tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "We have no core changes but lots of incremental development in drivers
  all over the place: Renesas, NXP, Mediatek and Actions Semiconductor
  keep churning out new SoCs.

  I have some subtree maintainers for Renesas and Intel helping out to
  keep down the load, it's been working smoothly (Samsung also have a
  subtree but it was not used this cycle.)

  New drivers:

   - NXP (ex Freescale) i.MX 8 QXP SoC driver.

   - Mediatek MT6797 SoC driver.

   - Mediatek MT7629 SoC driver.

   - Actions Semiconductor S700 SoC driver.

   - Renesas RZ/A2 SoC driver.

   - Allwinner sunxi suniv F1C100 SoC driver.

   - Qualcomm PMS405 PMIC driver.

   - Microsemi Ocelot Jaguar2 SoC driver.

  Improvements:

   - Some RT improvements (using raw spinlocks where appropriate).

   - A lot of new pin sets on the Renesas PFC pin controllers.

   - GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
     chips, and Xway.

   - Major modernization of the Intel pin control drivers.

   - STM32 pin control driver will now synchronize usage of pins with
     another CPU using a hardware spinlock"

* tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits)
  dt-bindings: arm: fsl-scu: add imx8qm pinctrl support
  pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ
  pinctrl: imx-scu: Depend on IMX_SCU
  pinctrl: ocelot: Add dependency on HAS_IOMEM
  pinctrl: ocelot: add MSCC Jaguar2 support
  pinctrl: bcm: ns: support updated DT binding as syscon subnode
  dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
  MAINTAINERS: merge at91 pinctrl entries
  pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
  pinctrl: uniphier: constify uniphier_pinctrl_socdata
  pinctrl: mediatek: improve Kconfig dependencies
  pinctrl: msm: mark PM functions as __maybe_unused
  dt-bindings: pinctrl: sunxi: Add supply properties
  pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
  pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
  pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
  pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
  pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
  pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
  pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
  ...
This commit is contained in:
Linus Torvalds 2019-01-01 13:19:16 -08:00
commit c9bef4a651
117 changed files with 14485 additions and 1405 deletions
Download patch file Download diff file Expand all files Collapse all files

17
drivers/pinctrl/Kconfig
View file

@ -195,6 +195,17 @@ config PINCTRL_RZA1
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "Renesas RZ/A2 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
@ -339,15 +350,15 @@ config PINCTRL_RK805
This selects the pinctrl driver for RK805.
config PINCTRL_OCELOT
bool "Pinctrl driver for the Microsemi Ocelot SoCs"
default y
bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
depends on OF
depends on MSCC_OCELOT || COMPILE_TEST
depends on HAS_IOMEM
select GPIOLIB
select GPIOLIB_IRQCHIP
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
select REGMAP_MMIO
source "drivers/pinctrl/actions/Kconfig"

1
drivers/pinctrl/Makefile
View file

@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/

6
drivers/pinctrl/actions/Kconfig
View file

@ -9,6 +9,12 @@ config PINCTRL_OWL
help
Say Y here to enable Actions Semi OWL pinctrl driver
config PINCTRL_S700
bool "Actions Semi S700 pinctrl driver"
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S700 pinctrl driver
config PINCTRL_S900
bool "Actions Semi S900 pinctrl driver"
depends on PINCTRL_OWL

1
drivers/pinctrl/actions/Makefile
View file

@ -1,2 +1,3 @@
obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o
obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o

71
drivers/pinctrl/actions/pinctrl-owl.c
View file

@ -246,60 +246,6 @@ static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
return 0;
}
static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = *arg == OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = *arg == OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
@ -318,7 +264,10 @@ static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
arg = owl_read_field(pctrl, reg, bit, width);
ret = owl_pad_pinconf_val2arg(info, param, &arg);
if (!pctrl->soc->padctl_val2arg)
return -ENOTSUPP;
ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
@ -349,7 +298,10 @@ static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
if (ret)
return ret;
ret = owl_pad_pinconf_arg2val(info, param, &arg);
if (!pctrl->soc->padctl_arg2val)
return -ENOTSUPP;
ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
@ -787,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data)
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_ENABLE, false);
OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
@ -811,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data)
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
<< port->shared_ctl_offset * 5);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
@ -849,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data)
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_PENDING, true);
OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}

142
drivers/pinctrl/actions/pinctrl-owl.h
View file

@ -15,12 +15,135 @@
#define OWL_PINCONF_SLEW_SLOW 0
#define OWL_PINCONF_SLEW_FAST 1
enum owl_pinconf_pull {
OWL_PINCONF_PULL_HIZ,
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
OWL_PINCONF_PULL_HOLD,
};
#define MUX_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.funcs = group_name##_funcs, \
.nfuncs = ARRAY_SIZE(group_name##_funcs), \
.mfpctl_reg = MFCTL##reg, \
.mfpctl_shift = shift, \
.mfpctl_width = width, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define DRV_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = PAD_DRV##reg, \
.drv_shift = shift, \
.drv_width = width, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define SR_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = PAD_SR##reg, \
.sr_shift = shift, \
.sr_width = width, \
}
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
/* PAD PULL UP/DOWN CONFIGURES */
#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
{ \
.reg = PAD_PULLCTL##pull_reg, \
.shift = pull_sft, \
.width = pull_wdt, \
}
#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
struct owl_pullctl pad_name##_pullctl_conf \
= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
#define ST_CONF(st_reg, st_sft, st_wdt) \
{ \
.reg = PAD_ST##st_reg, \
.shift = st_sft, \
.width = st_wdt, \
}
#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
struct owl_st pad_name##_st_conf \
= ST_CONF(st_reg, st_sft, st_wdt)
#define PAD_INFO(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = NULL, \
}
#define PAD_INFO_ST(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = &name##_st_conf, \
}
#define PAD_INFO_PULLCTL(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = NULL, \
}
#define PAD_INFO_PULLCTL_ST(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = &name##_st_conf, \
}
#define OWL_GPIO_PORT_A 0
#define OWL_GPIO_PORT_B 1
#define OWL_GPIO_PORT_C 2
#define OWL_GPIO_PORT_D 3
#define OWL_GPIO_PORT_E 4
#define OWL_GPIO_PORT_F 5
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
_intc_pd, _intc_msk, _intc_type, _share) \
[OWL_GPIO_PORT_##port] = { \
.offset = base, \
.pins = count, \
.outen = _outen, \
.inen = _inen, \
.dat = _dat, \
.intc_ctl = _intc_ctl, \
.intc_pd = _intc_pd, \
.intc_msk = _intc_msk, \
.intc_type = _intc_type, \
.shared_ctl_offset = _share, \
}
enum owl_pinconf_drv {
OWL_PINCONF_DRV_2MA,
@ -148,6 +271,7 @@ struct owl_gpio_port {
unsigned int intc_pd;
unsigned int intc_msk;
unsigned int intc_type;
u8 shared_ctl_offset;
};
/**
@ -174,6 +298,12 @@ struct owl_pinctrl_soc_data {
unsigned int ngpios;
const struct owl_gpio_port *ports;
unsigned int nports;
int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg);
int (*padctl_arg2val)(const struct owl_padinfo *info,
unsigned int param,
u32 *arg);
};
int owl_pinctrl_probe(struct platform_device *pdev,

1912
drivers/pinctrl/actions/pinctrl-s700.c Normal file
View file

File diff suppressed because it is too large Load diff

205
drivers/pinctrl/actions/pinctrl-s900.c
View file

@ -13,6 +13,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
@ -33,13 +34,6 @@
#define PAD_SR1 (0x0274)
#define PAD_SR2 (0x0278)
#define OWL_GPIO_PORT_A 0
#define OWL_GPIO_PORT_B 1
#define OWL_GPIO_PORT_C 2
#define OWL_GPIO_PORT_D 3
#define OWL_GPIO_PORT_E 4
#define OWL_GPIO_PORT_F 5
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
@ -892,55 +886,6 @@ static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
SENSOR0_CKOUT };
#define MUX_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.funcs = group_name##_funcs, \
.nfuncs = ARRAY_SIZE(group_name##_funcs), \
.mfpctl_reg = MFCTL##reg, \
.mfpctl_shift = shift, \
.mfpctl_width = width, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define DRV_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = PAD_DRV##reg, \
.drv_shift = shift, \
.drv_width = width, \
.sr_reg = -1, \
.sr_shift = -1, \
.sr_width = -1, \
}
#define SR_PG(group_name, reg, shift, width) \
{ \
.name = #group_name, \
.pads = group_name##_pads, \
.npads = ARRAY_SIZE(group_name##_pads), \
.mfpctl_reg = -1, \
.mfpctl_shift = -1, \
.mfpctl_width = -1, \
.drv_reg = -1, \
.drv_shift = -1, \
.drv_width = -1, \
.sr_reg = PAD_SR##reg, \
.sr_shift = shift, \
.sr_width = width, \
}
/* Pinctrl groups */
static const struct owl_pingroup s900_groups[] = {
@ -1442,13 +1387,6 @@ static const char * const sirq2_groups[] = {
"sirq2_dummy",
};
#define FUNCTION(fname) \
{ \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_ERAM] = FUNCTION(eram),
[S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
@ -1500,28 +1438,6 @@ static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_SIRQ1] = FUNCTION(sirq1),
[S900_MUX_SIRQ2] = FUNCTION(sirq2)
};
/* PAD PULL UP/DOWN CONFIGURES */
#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
{ \
.reg = PAD_PULLCTL##pull_reg, \
.shift = pull_sft, \
.width = pull_wdt, \
}
#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
struct owl_pullctl pad_name##_pullctl_conf \
= PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
#define ST_CONF(st_reg, st_sft, st_wdt) \
{ \
.reg = PAD_ST##st_reg, \
.shift = st_sft, \
.width = st_wdt, \
}
#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
struct owl_st pad_name##_st_conf \
= ST_CONF(st_reg, st_sft, st_wdt)
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
@ -1639,34 +1555,6 @@ static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
#define PAD_INFO(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = NULL, \
}
#define PAD_INFO_ST(name) \
{ \
.pad = name, \
.pullctl = NULL, \
.st = &name##_st_conf, \
}
#define PAD_INFO_PULLCTL(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = NULL, \
}
#define PAD_INFO_PULLCTL_ST(name) \
{ \
.pad = name, \
.pullctl = &name##_pullctl_conf, \
.st = &name##_st_conf, \
}
/* Pad info table */
static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
@ -1821,28 +1709,75 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
};
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
_intc_ctl, _intc_pd, _intc_msk, _intc_type) \
[OWL_GPIO_PORT_##port] = { \
.offset = base, \
.pins = count, \
.outen = _outen, \
.inen = _inen, \
.dat = _dat, \
.intc_ctl = _intc_ctl, \
.intc_pd = _intc_pd, \
.intc_msk = _intc_msk, \
.intc_type = _intc_type, \
static const struct owl_gpio_port s900_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
};
enum s900_pinconf_pull {
OWL_PINCONF_PULL_HIZ,
OWL_PINCONF_PULL_DOWN,
OWL_PINCONF_PULL_UP,
OWL_PINCONF_PULL_HOLD,
};
static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = (*arg >= 1 ? 1 : 0);
break;
default:
return -ENOTSUPP;
}
static const struct owl_gpio_port s900_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
};
return 0;
}
static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
unsigned int param,
u32 *arg)
{
switch (param) {
case PIN_CONFIG_BIAS_BUS_HOLD:
*arg = *arg == OWL_PINCONF_PULL_HOLD;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
*arg = *arg == OWL_PINCONF_PULL_HIZ;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
*arg = *arg == OWL_PINCONF_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_PULL_UP:
*arg = *arg == OWL_PINCONF_PULL_UP;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
*arg = *arg == 1;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.padinfo = s900_padinfo,
@ -1854,7 +1789,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.ngroups = ARRAY_SIZE(s900_groups),
.ngpios = NUM_GPIOS,
.ports = s900_gpio_ports,
.nports = ARRAY_SIZE(s900_gpio_ports)
.nports = ARRAY_SIZE(s900_gpio_ports),
.padctl_arg2val = s900_pad_pinconf_arg2val,
.padctl_val2arg = s900_pad_pinconf_val2arg,
};
static int s900_pinctrl_probe(struct platform_device *pdev)

2
drivers/pinctrl/aspeed/Makefile
View file

@ -1,6 +1,6 @@
# Aspeed pinctrl support
ccflags-y += -Woverride-init
ccflags-y += $(call cc-option,-Woverride-init)
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o

33
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View file

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
*
@ -6,16 +7,6 @@
* This driver is inspired by:
* pinctrl-nomadik.c, please see original file for copyright information
* pinctrl-tegra.c, please see original file for copyright information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/bitmap.h>
@ -72,10 +63,8 @@
#define GPIO_REG_OFFSET(p) ((p) / 32)
#define GPIO_REG_SHIFT(p) ((p) % 32)
enum bcm2835_pinconf_param {
/* argument: bcm2835_pinconf_pull */
BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1),
};
/* argument: bcm2835_pinconf_pull */
#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
struct bcm2835_pinctrl {
struct device *dev;
@ -90,7 +79,7 @@ struct bcm2835_pinctrl {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
spinlock_t irq_lock[BCM2835_NUM_BANKS];
raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
};
/* pins are just named GPIO0..GPIO53 */
@ -461,10 +450,10 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
set_bit(offset, &pc->enabled_irq_map[bank]);
bcm2835_gpio_irq_config(pc, gpio, true);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static void bcm2835_gpio_irq_disable(struct irq_data *data)
@ -476,12 +465,12 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
bcm2835_gpio_irq_config(pc, gpio, false);
/* Clear events that were latched prior to clearing event sources */
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
clear_bit(offset, &pc->enabled_irq_map[bank]);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
@ -584,7 +573,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
unsigned long flags;
int ret;
spin_lock_irqsave(&pc->irq_lock[bank], flags);
raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
if (test_bit(offset, &pc->enabled_irq_map[bank]))
ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
@ -596,7 +585,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
else
irq_set_handler_locked(data, handle_level_irq);
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
return ret;
}
@ -1047,7 +1036,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
for_each_set_bit(offset, &events, 32)
bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
spin_lock_init(&pc->irq_lock[i]);
raw_spin_lock_init(&pc->irq_lock[i]);
}
err = gpiochip_add_data(&pc->gpio_chip, pc);

29
drivers/pinctrl/bcm/pinctrl-ns.c
View file

@ -5,6 +5,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -12,6 +13,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define FLAG_BCM4708 BIT(1)
@ -22,7 +24,8 @@ struct ns_pinctrl {
struct device *dev;
unsigned int chipset_flag;
struct pinctrl_dev *pctldev;
void __iomem *base;
struct regmap *regmap;
u32 offset;
struct pinctrl_desc pctldesc;
struct ns_pinctrl_group *groups;
@ -229,9 +232,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
unset |= BIT(pin_number);
}
tmp = readl(ns_pinctrl->base);
regmap_read(ns_pinctrl->regmap, ns_pinctrl->offset, &tmp);
tmp &= ~unset;
writel(tmp, ns_pinctrl->base);
regmap_write(ns_pinctrl->regmap, ns_pinctrl->offset, tmp);
return 0;
}
@ -263,13 +266,13 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = {
static int ns_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
const struct of_device_id *of_id;
struct ns_pinctrl *ns_pinctrl;
struct pinctrl_desc *pctldesc;
struct pinctrl_pin_desc *pin;
struct ns_pinctrl_group *group;
struct ns_pinctrl_function *function;
struct resource *res;
int i;
ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
@ -287,12 +290,18 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
return -EINVAL;
ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
ns_pinctrl->base = devm_ioremap_resource(dev, res);
if (IS_ERR(ns_pinctrl->base)) {
dev_err(dev, "Failed to map pinctrl regs\n");
return PTR_ERR(ns_pinctrl->base);
ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np));
if (IS_ERR(ns_pinctrl->regmap)) {
int err = PTR_ERR(ns_pinctrl->regmap);
dev_err(dev, "Failed to map pinctrl regs: %d\n", err);
return err;
}
if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) {
dev_err(dev, "Failed to get register offset\n");
return -ENOENT;
}
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));

14
drivers/pinctrl/freescale/Kconfig
View file

@ -5,6 +5,11 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
config PINCTRL_IMX_SCU
bool
depends on IMX_SCU
select PINCTRL_IMX
config PINCTRL_IMX1_CORE
bool
select PINMUX
@ -119,11 +124,18 @@ config PINCTRL_IMX7ULP
config PINCTRL_IMX8MQ
bool "IMX8MQ pinctrl driver"
depends on SOC_IMX8MQ
depends on ARCH_MXC && ARM64
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_IMX8QXP
bool "IMX8QXP pinctrl driver"
depends on ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qxp pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610

2
drivers/pinctrl/freescale/Makefile
View file

@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
@ -18,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

436
drivers/pinctrl/freescale/pinctrl-imx.c
View file

@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
struct imx_pin *pin;
int map_num = 1;
int i, j;
@ -73,11 +75,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
for (i = 0; i < grp->num_pins; i++) {
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
if (!(pin->config & IMX_NO_PAD_CTL))
map_num++;
if (info->flags & IMX_USE_SCU) {
map_num += grp->num_pins;
} else {
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
map_num++;
}
}
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
@ -102,16 +107,35 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
pin = &((struct imx_pin *)(grp->data))[i];
if (!(pin->config & IMX_NO_PAD_CTL)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
/*
* We only create config maps for SCU pads or MMIO pads that
* are not using the default config(a.k.a IMX_NO_PAD_CTL)
*/
if (!(info->flags & IMX_USE_SCU) &&
(pin->conf.mmio.config & IMX_NO_PAD_CTL))
continue;
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
new_map[j].data.configs.configs = &pin->config;
if (info->flags & IMX_USE_SCU) {
/*
* For SCU case, we set mux and conf together
* in one IPC call
*/
new_map[j].data.configs.configs =
(unsigned long *)&pin->conf.scu;
new_map[j].data.configs.num_configs = 2;
} else {
new_map[j].data.configs.configs =
&pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
j++;
}
j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
@ -133,19 +157,96 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
};
static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
struct imx_pin *pin)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
const struct imx_pin_reg *pin_reg;
unsigned int pin_id;
pin_id = pin->pin;
pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->mux_reg == -1) {
dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
return 0;
}
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~info->mux_mask;
reg |= (pin_mmio->mux_mode << info->mux_shift);
writel(reg, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, reg);
} else {
writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, pin_mmio->mux_mode);
}
/*
* If the select input value begins with 0xff, it's a quirky
* select input and the value should be interpreted as below.
* 31 23 15 7 0
* | 0xff | shift | width | select |
* It's used to work around the problem that the select
* input for some pin is not implemented in the select
* input register but in some general purpose register.
* We encode the select input value, width and shift of
* the bit field into input_val cell of pin function ID
* in device tree, and then decode them here for setting
* up the select input bits in general purpose register.
*/
if (pin_mmio->input_val >> 24 == 0xff) {
u32 val = pin_mmio->input_val;
u8 select = val & 0xff;
u8 width = (val >> 8) & 0xff;
u8 shift = (val >> 16) & 0xff;
u32 mask = ((1 << width) - 1) << shift;
/*
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
val = readl(ipctl->base + pin_mmio->input_reg);
val &= ~mask;
val |= select << shift;
writel(val, ipctl->base + pin_mmio->input_reg);
} else if (pin_mmio->input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
if (ipctl->input_sel_base)
writel(pin_mmio->input_val, ipctl->input_sel_base +
pin_mmio->input_reg);
else
writel(pin_mmio->input_val, ipctl->base +
pin_mmio->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin_mmio->input_reg, pin_mmio->input_val);
}
return 0;
}
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
unsigned int npins, pin_id;
int i;
struct group_desc *grp = NULL;
struct function_desc *func = NULL;
struct function_desc *func;
struct group_desc *grp;
struct imx_pin *pin;
unsigned int npins;
int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@ -165,72 +266,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
pin_id = pin->pin;
pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->mux_reg == -1) {
dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
continue;
}
if (info->flags & SHARE_MUX_CONF_REG) {
u32 reg;
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~info->mux_mask;
reg |= (pin->mux_mode << info->mux_shift);
writel(reg, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, reg);
} else {
writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, pin->mux_mode);
}
/*
* If the select input value begins with 0xff, it's a quirky
* select input and the value should be interpreted as below.
* 31 23 15 7 0
* | 0xff | shift | width | select |
* It's used to work around the problem that the select
* input for some pin is not implemented in the select
* input register but in some general purpose register.
* We encode the select input value, width and shift of
* the bit field into input_val cell of pin function ID
* in device tree, and then decode them here for setting
* up the select input bits in general purpose register.
* For IMX_USE_SCU case, we postpone the mux setting
* until config is set as we can set them together
* in one IPC call
*/
if (pin->input_val >> 24 == 0xff) {
u32 val = pin->input_val;
u8 select = val & 0xff;
u8 width = (val >> 8) & 0xff;
u8 shift = (val >> 16) & 0xff;
u32 mask = ((1 << width) - 1) << shift;
/*
* The input_reg[i] here is actually some IOMUXC general
* purpose register, not regular select input register.
*/
val = readl(ipctl->base + pin->input_reg);
val &= ~mask;
val |= select << shift;
writel(val, ipctl->base + pin->input_reg);
} else if (pin->input_reg) {
/*
* Regular select input register can never be at offset
* 0, and we only print register value for regular case.
*/
if (ipctl->input_sel_base)
writel(pin->input_val, ipctl->input_sel_base +
pin->input_reg);
else
writel(pin->input_val, ipctl->base +
pin->input_reg);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
pin->input_reg, pin->input_val);
pin = &((struct imx_pin *)(grp->data))[i];
if (!(info->flags & IMX_USE_SCU)) {
err = imx_pmx_set_one_pin_mmio(ipctl, pin);
if (err)
return err;
}
}
@ -300,8 +345,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@ -321,9 +366,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_get_scu(pctldev, pin_id, config);
else
return imx_pinconf_get_mmio(pctldev, pin_id, config);
}
static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@ -358,19 +415,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_set_scu(pctldev, pin_id,
configs, num_configs);
else
return imx_pinconf_set_mmio(pctldev, pin_id,
configs, num_configs);
}
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
unsigned long config;
int ret;
if (!pin_reg || pin_reg->conf_reg == -1) {
seq_puts(s, "N/A");
return;
if (info->flags & IMX_USE_SCU) {
ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
if (ret) {
dev_err(ipctl->dev, "failed to get %s pinconf\n",
pin_get_name(pctldev, pin_id));
seq_puts(s, "N/A");
return;
}
} else {
pin_reg = &ipctl->pin_regs[pin_id];
if (!pin_reg || pin_reg->conf_reg == -1) {
seq_puts(s, "N/A");
return;
}
config = readl(ipctl->base + pin_reg->conf_reg);
}
config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@ -418,9 +504,65 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
* IMX_USE_SCU:
* <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
#define FSL_SCU_PIN_SIZE 12
static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p,
struct device_node *np)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
struct imx_pin_reg *pin_reg;
const __be32 *list = *list_p;
u32 mux_reg, conf_reg;
u32 config;
mux_reg = be32_to_cpu(*list++);
if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
mux_reg = -1;
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
if (!conf_reg)
conf_reg = -1;
}
*pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = &ipctl->pin_regs[*pin_id];
pin->pin = *pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
pin_mmio->input_reg = be32_to_cpu(*list++);
pin_mmio->mux_mode = be32_to_cpu(*list++);
pin_mmio->input_val = be32_to_cpu(*list++);
if (info->generic_pinconf) {
/* generic pin config decoded */
pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
} else {
/* legacy pin config read from devicetree */
config = be32_to_cpu(*list++);
/* SION bit is in mux register */
if (config & IMX_PAD_SION)
pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
pin_mmio->config = config & ~IMX_PAD_SION;
}
*list_p = list;
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
pin_mmio->mux_mode, pin_mmio->config);
}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@ -428,14 +570,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
u32 config;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
if (info->flags & SHARE_MUX_CONF_REG)
if (info->flags & IMX_USE_SCU)
pin_size = FSL_SCU_PIN_SIZE;
else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@ -472,9 +616,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
/* first try to parse the generic pin config */
config = imx_pinconf_parse_generic_config(np, ipctl);
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
@ -486,48 +627,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
u32 conf_reg;
unsigned int pin_id;
struct imx_pin_reg *pin_reg;
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
mux_reg = -1;
if (info->flags & SHARE_MUX_CONF_REG) {
conf_reg = mux_reg;
} else {
conf_reg = be32_to_cpu(*list++);
if (!conf_reg)
conf_reg = -1;
}
pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
pin_reg = &ipctl->pin_regs[pin_id];
pin->pin = pin_id;
grp->pins[i] = pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
pin->input_reg = be32_to_cpu(*list++);
pin->mux_mode = be32_to_cpu(*list++);
pin->input_val = be32_to_cpu(*list++);
if (info->generic_pinconf) {
/* generic pin config decoded */
pin->config = config;
} else {
/* legacy pin config read from devicetree */
config = be32_to_cpu(*list++);
/* SION bit is in mux register */
if (config & IMX_PAD_SION)
pin->mux_mode |= IOMUXC_CONFIG_SION;
pin->config = config & ~IMX_PAD_SION;
}
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
pin->mux_mode, pin->config);
pin = &((struct imx_pin *)(grp->data))[i];
if (info->flags & IMX_USE_SCU)
imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
pin, &list);
else
imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
pin, &list, np);
}
return 0;
@ -699,35 +805,37 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
info->npins, sizeof(*ipctl->pin_regs),
GFP_KERNEL);
if (!ipctl->pin_regs)
return -ENOMEM;
if (!(info->flags & IMX_USE_SCU)) {
ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
sizeof(*ipctl->pin_regs),
GFP_KERNEL);
if (!ipctl->pin_regs)
return -ENOMEM;
for (i = 0; i < info->npins; i++) {
ipctl->pin_regs[i].mux_reg = -1;
ipctl->pin_regs[i].conf_reg = -1;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
if (of_property_read_bool(dev_np, "fsl,input-sel")) {
np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
if (!np) {
dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
return -EINVAL;
for (i = 0; i < info->npins; i++) {
ipctl->pin_regs[i].mux_reg = -1;
ipctl->pin_regs[i].conf_reg = -1;
}
ipctl->input_sel_base = of_iomap(np, 0);
of_node_put(np);
if (!ipctl->input_sel_base) {
dev_err(&pdev->dev,
"iomuxc input select base address not found\n");
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
if (of_property_read_bool(dev_np, "fsl,input-sel")) {
np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
if (!np) {
dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
return -EINVAL;
}
ipctl->input_sel_base = of_iomap(np, 0);
of_node_put(np);
if (!ipctl->input_sel_base) {
dev_err(&pdev->dev,
"iomuxc input select base address not found\n");
return -ENOMEM;
}
}
}

67
drivers/pinctrl/freescale/pinctrl-imx.h
View file

@ -19,22 +19,43 @@ struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
* struct imx_pin - describes a single i.MX pin
* @pin: the pin_id of this pin
* struct imx_pin_mmio - MMIO pin configurations
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
struct imx_pin {
unsigned int pin;
struct imx_pin_mmio {
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
unsigned long config;
};
/**
* struct imx_pin_scu - SCU pin configurations
* @mux: the mux mode for this pin.
* @configs: the config for this pin.
*/
struct imx_pin_scu {
unsigned int mux_mode;
unsigned long config;
};
/**
* struct imx_pin - describes a single i.MX pin
* @pin: the pin_id of this pin
* @conf: config type of this pin, either mmio or scu
*/
struct imx_pin {
unsigned int pin;
union {
struct imx_pin_mmio mmio;
struct imx_pin_scu scu;
} conf;
};
/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
@ -99,8 +120,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
#define SHARE_MUX_CONF_REG BIT(0)
#define ZERO_OFFSET_VALID BIT(1)
#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@ -113,4 +135,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
#ifdef CONFIG_PINCTRL_IMX_SCU
#define BM_PAD_CTL_GP_ENABLE BIT(30)
#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
#define BP_PAD_CTL_IFMUX 27
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config);
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs);
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
#else
static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
return -EINVAL;
}
static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
return -EINVAL;
}
static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id,
struct imx_pin *pin,
const __be32 **list_p)
{
}
#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */

42
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
View file

@ -256,46 +256,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_LK_ENABLED BIT(15)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
#define BM_PULL_ENABLED BIT(1)
static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0),
};
static void imx7ulp_cfg_params_fixup(unsigned long *configs,
unsigned int num_configs,
u32 *raw_config)
{
enum pin_config_param param;
u32 param_val;
int i;
/* lock field disabled */
*raw_config &= ~BM_LK_ENABLED;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
(param == PIN_CONFIG_BIAS_PULL_DOWN)) {
/* pull enabled */
*raw_config |= BM_PULL_ENABLED;
return;
}
}
}
static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
@ -326,10 +288,6 @@ static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
.generic_pinconf = true,
.decodes = imx7ulp_cfg_decodes,
.num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
.fixup = imx7ulp_cfg_params_fixup,
};
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {

232
drivers/pinctrl/freescale/pinctrl-imx8qxp.c Normal file
View file

@ -0,0 +1,232 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
};
static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,
};
static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", },
{ /* sentinel */ }
};
static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
{
int ret;
ret = imx_pinctrl_sc_ipc_init(pdev);
if (ret)
return ret;
return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
}
static struct platform_driver imx8qxp_pinctrl_driver = {
.driver = {
.name = "imx8qxp-pinctrl",
.of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imx8qxp_pinctrl_probe,
};
static int __init imx8qxp_pinctrl_init(void)
{
return platform_driver_register(&imx8qxp_pinctrl_driver);
}
arch_initcall(imx8qxp_pinctrl_init);

121
drivers/pinctrl/freescale/pinctrl-scu.c Normal file
View file

@ -0,0 +1,121 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include "../core.h"
#include "pinctrl-imx.h"
enum pad_func_e {
IMX_SC_PAD_FUNC_SET = 15,
IMX_SC_PAD_FUNC_GET = 16,
};
struct imx_sc_msg_req_pad_set {
struct imx_sc_rpc_msg hdr;
u32 val;
u16 pad;
} __packed;
struct imx_sc_msg_req_pad_get {
struct imx_sc_rpc_msg hdr;
u16 pad;
} __packed;
struct imx_sc_msg_resp_pad_get {
struct imx_sc_rpc_msg hdr;
u32 val;
} __packed;
struct imx_sc_ipc *pinctrl_ipc_handle;
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
{
return imx_scu_get_handle(&pinctrl_ipc_handle);
}
int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *config)
{
struct imx_sc_msg_req_pad_get msg;
struct imx_sc_msg_resp_pad_get *resp;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_GET;
hdr->size = 2;
msg.pad = pin_id;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
if (ret)
return ret;
resp = (struct imx_sc_msg_resp_pad_get *)&msg;
*config = resp->val;
return 0;
}
int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
unsigned long *configs, unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_sc_msg_req_pad_set msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
unsigned int mux = configs[0];
unsigned int conf = configs[1];
unsigned int val;
int ret;
/*
* Set mux and conf together in one IPC call
*/
WARN_ON(num_configs != 2);
val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
val |= mux << BP_PAD_CTL_IFMUX;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PAD;
hdr->func = IMX_SC_PAD_FUNC_SET;
hdr->size = 3;
msg.pad = pin_id;
msg.val = val;
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
pin_id, conf, val);
return ret;
}
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_pin_scu *pin_scu = &pin->conf.scu;
const __be32 *list = *list_p;
pin->pin = be32_to_cpu(*list++);
*pin_id = pin->pin;
pin_scu->mux_mode = be32_to_cpu(*list++);
pin_scu->config = be32_to_cpu(*list++);
*list_p = list;
dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
pin_scu->mux_mode, pin_scu->config);
}

8
drivers/pinctrl/intel/pinctrl-baytrail.c
View file

@ -705,7 +705,7 @@ static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
&byt_score_soc_data,
&byt_sus_soc_data,
&byt_ncore_soc_data,
NULL,
NULL
};
static struct byt_community *byt_get_community(struct byt_gpio *vg,
@ -1838,8 +1838,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int byt_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
struct byt_gpio *vg = dev_get_drvdata(dev);
int i;
for (i = 0; i < vg->soc_data->npins; i++) {
@ -1867,8 +1866,7 @@ static int byt_gpio_suspend(struct device *dev)
static int byt_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct byt_gpio *vg = platform_get_drvdata(pdev);
struct byt_gpio *vg = dev_get_drvdata(dev);
int i;
for (i = 0; i < vg->soc_data->npins; i++) {

13
drivers/pinctrl/intel/pinctrl-broxton.c
View file

@ -526,7 +526,7 @@ static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
&bxt_west_soc_data,
&bxt_southwest_soc_data,
&bxt_south_soc_data,
NULL,
NULL
};
/* APL */
@ -990,7 +990,7 @@ static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
&apl_northwest_soc_data,
&apl_west_soc_data,
&apl_southwest_soc_data,
NULL,
NULL
};
static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
@ -1003,18 +1003,13 @@ MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
{ "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
{ "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
{ },
{ }
};
static int bxt_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_uid(pdev);
}
static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
static struct platform_driver bxt_pinctrl_driver = {
.probe = bxt_pinctrl_probe,
.probe = intel_pinctrl_probe_by_uid,
.driver = {
.name = "broxton-pinctrl",
.acpi_match_table = bxt_pinctrl_acpi_match,

9
drivers/pinctrl/intel/pinctrl-cannonlake.c
View file

@ -829,19 +829,14 @@ static const struct intel_pinctrl_soc_data cnllp_soc_data = {
static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
{ "INT3450", (kernel_ulong_t)&cnlh_soc_data },
{ "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
{ },
{ }
};
MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
static int cnl_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_hid(pdev);
}
static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
static struct platform_driver cnl_pinctrl_driver = {
.probe = cnl_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cannonlake-pinctrl",
.acpi_match_table = cnl_pinctrl_acpi_match,

11
drivers/pinctrl/intel/pinctrl-cedarfork.c
View file

@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@ -330,21 +330,16 @@ static const struct intel_pinctrl_soc_data cdf_soc_data = {
.ncommunities = ARRAY_SIZE(cdf_communities),
};
static int cdf_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &cdf_soc_data);
}
static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
{ "INTC3001" },
{ "INTC3001", (kernel_ulong_t)&cdf_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
static struct platform_driver cdf_pinctrl_driver = {
.probe = cdf_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "cedarfork-pinctrl",
.acpi_match_table = cdf_pinctrl_acpi_match,

32
drivers/pinctrl/intel/pinctrl-cherryview.c
View file

@ -846,6 +846,19 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
return 0;
}
static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
unsigned int offset)
{
void __iomem *reg;
u32 value;
reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
value = readl(reg);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
chv_writel(value, reg);
}
static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
@ -876,11 +889,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
}
/* Disable interrupt generation */
reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
value = readl(reg);
value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
value &= ~CHV_PADCTRL1_INVRXTX_MASK;
chv_writel(value, reg);
chv_gpio_clear_triggering(pctrl, offset);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg);
@ -912,14 +921,11 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
void __iomem *reg;
u32 value;
raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
chv_writel(value, reg);
if (!chv_pad_locked(pctrl, offset))
chv_gpio_clear_triggering(pctrl, offset);
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
@ -1744,8 +1750,7 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
unsigned long flags;
int i;
@ -1778,8 +1783,7 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
unsigned long flags;
int i;

11
drivers/pinctrl/intel/pinctrl-denverton.c
View file

@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@ -257,21 +257,16 @@ static const struct intel_pinctrl_soc_data dnv_soc_data = {
.ncommunities = ARRAY_SIZE(dnv_communities),
};
static int dnv_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &dnv_soc_data);
}
static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000" },
{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
static struct platform_driver dnv_pinctrl_driver = {
.probe = dnv_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "denverton-pinctrl",
.acpi_match_table = dnv_pinctrl_acpi_match,

2
drivers/pinctrl/intel/pinctrl-geminilake.c
View file

@ -445,7 +445,7 @@ static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
&glk_north_soc_data,
&glk_audio_soc_data,
&glk_scc_soc_data,
NULL,
NULL
};
static const struct acpi_device_id glk_pinctrl_acpi_match[] = {

11
drivers/pinctrl/intel/pinctrl-icelake.c
View file

@ -403,21 +403,16 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = {
.ncommunities = ARRAY_SIZE(icllp_communities),
};
static int icl_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &icllp_soc_data);
}
static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455" },
{ },
{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
static struct platform_driver icl_pinctrl_driver = {
.probe = icl_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "icelake-pinctrl",
.acpi_match_table = icl_pinctrl_acpi_match,

11
drivers/pinctrl/intel/pinctrl-intel.c
View file

@ -1301,8 +1301,8 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
struct intel_pinctrl *pctrl;
int i, ret, irq;
@ -1400,7 +1400,6 @@ int intel_pinctrl_probe(struct platform_device *pdev,
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
{
@ -1469,8 +1468,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
int intel_pinctrl_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *communities;
struct intel_pad_context *pads;
int i;
@ -1531,8 +1529,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
int intel_pinctrl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
const struct intel_community_context *communities;
const struct intel_pad_context *pads;
int i;

2
drivers/pinctrl/intel/pinctrl-intel.h
View file

@ -173,8 +173,6 @@ struct intel_pinctrl_soc_data {
size_t ncommunities;
};
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);

11
drivers/pinctrl/intel/pinctrl-lewisburg.c
View file

@ -6,7 +6,7 @@
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@ -308,21 +308,16 @@ static const struct intel_pinctrl_soc_data lbg_soc_data = {
.ncommunities = ARRAY_SIZE(lbg_communities),
};
static int lbg_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &lbg_soc_data);
}
static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536" },
{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
static struct platform_driver lbg_pinctrl_driver = {
.probe = lbg_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "lewisburg-pinctrl",
.acpi_match_table = lbg_pinctrl_acpi_match,

2
drivers/pinctrl/intel/pinctrl-merrifield.c
View file

@ -6,7 +6,7 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>

7
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View file

@ -591,15 +591,10 @@ static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
static int spt_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe_by_hid(pdev);
}
static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
static struct platform_driver spt_pinctrl_driver = {
.probe = spt_pinctrl_probe,
.probe = intel_pinctrl_probe_by_hid,
.driver = {
.name = "sunrisepoint-pinctrl",
.acpi_match_table = spt_pinctrl_acpi_match,

27
drivers/pinctrl/mediatek/Kconfig
View file

@ -3,7 +3,7 @@ menu "MediaTek pinctrl drivers"
config EINT_MTK
bool "MediaTek External Interrupt Support"
depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST
select GPIOLIB
select IRQ_DOMAIN
@ -17,7 +17,7 @@ config PINCTRL_MTK
select OF_GPIO
config PINCTRL_MTK_MOORE
bool "MediaTek Moore Core that implements generic binding"
bool
depends on OF
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
@ -26,7 +26,7 @@ config PINCTRL_MTK_MOORE
select OF_GPIO
config PINCTRL_MTK_PARIS
bool "MediaTek Paris Core that implements vendor binding"
bool
depends on OF
select PINMUX
select GENERIC_PINCONF
@ -45,8 +45,14 @@ config PINCTRL_MT2701
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control with generic binding"
depends on MACH_MT7623 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
default MACH_MT7623
select PINCTRL_MTK_MOORE
config PINCTRL_MT7629
bool "Mediatek MT7629 pin control"
depends on MACH_MT7629 || COMPILE_TEST
default MACH_MT7629
select PINCTRL_MTK_MOORE
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
@ -77,11 +83,18 @@ config PINCTRL_MT6765
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT6797
bool "Mediatek MT6797 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MTK_MOORE
default y
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"

2
drivers/pinctrl/mediatek/Makefile
View file

@ -11,8 +11,10 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

4
drivers/pinctrl/mediatek/pinctrl-moore.c
View file

@ -310,8 +310,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
if (err)
return err;
} else {
err = -ENOTSUPP;
}

82
drivers/pinctrl/mediatek/pinctrl-mt6797.c Normal file
View file

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on pinctrl-mt6765.c
*
* Copyright (C) 2018 MediaTek Inc.
*
* Author: ZH Chen <zh.chen@mediatek.com>
*
* Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*
*/
#include "pinctrl-mtk-mt6797.h"
#include "pinctrl-paris.h"
/*
* MT6797 have multiple bases to program pin configuration listed as the below:
* gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
* iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
* _i_base could be used to indicate what base the pin should be mapped into.
*/
static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
};
static const char * const mt6797_pinctrl_register_base_names[] = {
"gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
};
static const struct mtk_pin_soc mt6797_data = {
.reg_cal = mt6797_reg_cals,
.pins = mtk_pins_mt6797,
.npins = ARRAY_SIZE(mtk_pins_mt6797),
.ngrps = ARRAY_SIZE(mtk_pins_mt6797),
.gpio_m = 0,
.base_names = mt6797_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
};
static const struct of_device_id mt6797_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt6797-pinctrl", },
{ }
};
static int mt6797_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
}
static struct platform_driver mt6797_pinctrl_driver = {
.driver = {
.name = "mt6797-pinctrl",
.of_match_table = mt6797_pinctrl_of_match,
},
.probe = mt6797_pinctrl_probe,
};
static int __init mt6797_pinctrl_init(void)
{
return platform_driver_register(&mt6797_pinctrl_driver);
}
arch_initcall(mt6797_pinctrl_init);

450
drivers/pinctrl/mediatek/pinctrl-mt7629.c Normal file
View file

@ -0,0 +1,450 @@
// SPDX-License-Identifier: GPL-2.0
/*
* The MT7629 driver based on Linux generic pinctrl binding.
*
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
#include "pinctrl-moore.h"
#define MT7629_PIN(_number, _name, _eint_n) \
MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
};
static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
};
static const struct mtk_pin_desc mt7629_pins[] = {
MT7629_PIN(0, "TOP_5G_CLK", 53),
MT7629_PIN(1, "TOP_5G_DATA", 54),
MT7629_PIN(2, "WF0_5G_HB0", 55),
MT7629_PIN(3, "WF0_5G_HB1", 56),
MT7629_PIN(4, "WF0_5G_HB2", 57),
MT7629_PIN(5, "WF0_5G_HB3", 58),
MT7629_PIN(6, "WF0_5G_HB4", 59),
MT7629_PIN(7, "WF0_5G_HB5", 60),
MT7629_PIN(8, "WF0_5G_HB6", 61),
MT7629_PIN(9, "XO_REQ", 9),
MT7629_PIN(10, "TOP_RST_N", 10),
MT7629_PIN(11, "SYS_WATCHDOG", 11),
MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
MT7629_PIN(17, "WF2G_LED_N", 17),
MT7629_PIN(18, "WF5G_LED_N", 18),
MT7629_PIN(19, "I2C_SDA", 19),
MT7629_PIN(20, "I2C_SCL", 20),
MT7629_PIN(21, "GPIO_9", 21),
MT7629_PIN(22, "GPIO_10", 22),
MT7629_PIN(23, "GPIO_11", 23),
MT7629_PIN(24, "GPIO_12", 24),
MT7629_PIN(25, "UART1_TXD", 25),
MT7629_PIN(26, "UART1_RXD", 26),
MT7629_PIN(27, "UART1_CTS", 27),
MT7629_PIN(28, "UART1_RTS", 28),
MT7629_PIN(29, "UART2_TXD", 29),
MT7629_PIN(30, "UART2_RXD", 30),
MT7629_PIN(31, "UART2_CTS", 31),
MT7629_PIN(32, "UART2_RTS", 32),
MT7629_PIN(33, "MDI_TP_P1", 33),
MT7629_PIN(34, "MDI_TN_P1", 34),
MT7629_PIN(35, "MDI_RP_P1", 35),
MT7629_PIN(36, "MDI_RN_P1", 36),
MT7629_PIN(37, "MDI_RP_P2", 37),
MT7629_PIN(38, "MDI_RN_P2", 38),
MT7629_PIN(39, "MDI_TP_P2", 39),
MT7629_PIN(40, "MDI_TN_P2", 40),
MT7629_PIN(41, "MDI_TP_P3", 41),
MT7629_PIN(42, "MDI_TN_P3", 42),
MT7629_PIN(43, "MDI_RP_P3", 43),
MT7629_PIN(44, "MDI_RN_P3", 44),
MT7629_PIN(45, "MDI_RP_P4", 45),
MT7629_PIN(46, "MDI_RN_P4", 46),
MT7629_PIN(47, "MDI_TP_P4", 47),
MT7629_PIN(48, "MDI_TN_P4", 48),
MT7629_PIN(49, "SMI_MDC", 49),
MT7629_PIN(50, "SMI_MDIO", 50),
MT7629_PIN(51, "PCIE_PERESET_N", 51),
MT7629_PIN(52, "PWM_0", 52),
MT7629_PIN(53, "GPIO_0", 0),
MT7629_PIN(54, "GPIO_1", 1),
MT7629_PIN(55, "GPIO_2", 2),
MT7629_PIN(56, "GPIO_3", 3),
MT7629_PIN(57, "GPIO_4", 4),
MT7629_PIN(58, "GPIO_5", 5),
MT7629_PIN(59, "GPIO_6", 6),
MT7629_PIN(60, "GPIO_7", 7),
MT7629_PIN(61, "GPIO_8", 8),
MT7629_PIN(62, "SPI_CLK", 62),
MT7629_PIN(63, "SPI_CS", 63),
MT7629_PIN(64, "SPI_MOSI", 64),
MT7629_PIN(65, "SPI_MISO", 65),
MT7629_PIN(66, "SPI_WP", 66),
MT7629_PIN(67, "SPI_HOLD", 67),
MT7629_PIN(68, "UART0_TXD", 68),
MT7629_PIN(69, "UART0_RXD", 69),
MT7629_PIN(70, "TOP_2G_CLK", 70),
MT7629_PIN(71, "TOP_2G_DATA", 71),
MT7629_PIN(72, "WF0_2G_HB0", 72),
MT7629_PIN(73, "WF0_2G_HB1", 73),
MT7629_PIN(74, "WF0_2G_HB2", 74),
MT7629_PIN(75, "WF0_2G_HB3", 75),
MT7629_PIN(76, "WF0_2G_HB4", 76),
MT7629_PIN(77, "WF0_2G_HB5", 77),
MT7629_PIN(78, "WF0_2G_HB6", 78),
};
/* List all groups consisting of these pins dedicated to the enablement of
* certain hardware block and the corresponding mode for all of the pins.
* The hardware probably has multiple combinations of these pinouts.
*/
/* LED for EPHY */
static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
static int mt7629_ephy_led0_pins[] = { 12, };
static int mt7629_ephy_led0_funcs[] = { 1, };
static int mt7629_ephy_led1_pins[] = { 13, };
static int mt7629_ephy_led1_funcs[] = { 1, };
static int mt7629_ephy_led2_pins[] = { 14, };
static int mt7629_ephy_led2_funcs[] = { 1, };
static int mt7629_ephy_led3_pins[] = { 15, };
static int mt7629_ephy_led3_funcs[] = { 1, };
static int mt7629_ephy_led4_pins[] = { 16, };
static int mt7629_ephy_led4_funcs[] = { 1, };
static int mt7629_wf2g_led_pins[] = { 17, };
static int mt7629_wf2g_led_funcs[] = { 1, };
static int mt7629_wf5g_led_pins[] = { 18, };
static int mt7629_wf5g_led_funcs[] = { 1, };
/* Watchdog */
static int mt7629_watchdog_pins[] = { 11, };
static int mt7629_watchdog_funcs[] = { 1, };
/* LED for GPHY */
static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
static int mt7629_gphy_led1_0_pins[] = { 21, };
static int mt7629_gphy_led1_0_funcs[] = { 2, };
static int mt7629_gphy_led2_0_pins[] = { 22, };
static int mt7629_gphy_led2_0_funcs[] = { 2, };
static int mt7629_gphy_led3_0_pins[] = { 23, };
static int mt7629_gphy_led3_0_funcs[] = { 2, };
static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
static int mt7629_gphy_led1_1_pins[] = { 57, };
static int mt7629_gphy_led1_1_funcs[] = { 1, };
static int mt7629_gphy_led2_1_pins[] = { 58, };
static int mt7629_gphy_led2_1_funcs[] = { 1, };
static int mt7629_gphy_led3_1_pins[] = { 59, };
static int mt7629_gphy_led3_1_funcs[] = { 1, };
/* I2C */
static int mt7629_i2c_0_pins[] = { 19, 20, };
static int mt7629_i2c_0_funcs[] = { 1, 1, };
static int mt7629_i2c_1_pins[] = { 53, 54, };
static int mt7629_i2c_1_funcs[] = { 1, 1, };
/* SPI */
static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
static int mt7629_spi_wp_pins[] = { 66, };
static int mt7629_spi_wp_funcs[] = { 1, };
static int mt7629_spi_hold_pins[] = { 67, };
static int mt7629_spi_hold_funcs[] = { 1, };
/* UART */
static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
/* MDC/MDIO */
static int mt7629_mdc_mdio_pins[] = { 49, 50, };
static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
/* PCIE */
static int mt7629_pcie_pereset_pins[] = { 51, };
static int mt7629_pcie_pereset_funcs[] = { 1, };
static int mt7629_pcie_wake_pins[] = { 55, };
static int mt7629_pcie_wake_funcs[] = { 1, };
static int mt7629_pcie_clkreq_pins[] = { 56, };
static int mt7629_pcie_clkreq_funcs[] = { 1, };
/* PWM */
static int mt7629_pwm_0_pins[] = { 52, };
static int mt7629_pwm_0_funcs[] = { 1, };
static int mt7629_pwm_1_pins[] = { 61, };
static int mt7629_pwm_1_funcs[] = { 2, };
/* WF 2G */
static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
/* WF 5G */
static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
/* SNFI */
static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
/* SPI NOR */
static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
static const struct group_desc mt7629_groups[] = {
PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
};
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
"ephy_led1", "ephy_led2",
"ephy_led3", "ephy_led4",
"wf2g_led", "wf5g_led",
"gphy_leds_0", "gphy_led1_0",
"gphy_led2_0", "gphy_led3_0",
"gphy_leds_1", "gphy_led1_1",
"gphy_led2_1", "gphy_led3_1",};
static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
"pcie_clkreq", };
static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
"spi_hold", };
static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
"uart1_1_txd_rxd",
"uart2_0_txd_rxd",
"uart2_1_txd_rxd",
"uart1_0_cts_rts",
"uart1_1_cts_rts",
"uart2_0_cts_rts",
"uart2_1_cts_rts",
"uart0_txd_rxd", };
static const char *mt7629_wdt_groups[] = { "watchdog", };
static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
static const struct function_desc mt7629_functions[] = {
{"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
{"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
{"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
{"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
{"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
{"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
{"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
{"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
{"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
{"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
};
static const struct mtk_eint_hw mt7629_eint_hw = {
.port_mask = 7,
.ports = 7,
.ap_num = ARRAY_SIZE(mt7629_pins),
.db_cnt = 16,
};
static struct mtk_pin_soc mt7629_data = {
.reg_cal = mt7629_reg_cals,
.pins = mt7629_pins,
.npins = ARRAY_SIZE(mt7629_pins),
.grps = mt7629_groups,
.ngrps = ARRAY_SIZE(mt7629_groups),
.funcs = mt7629_functions,
.nfuncs = ARRAY_SIZE(mt7629_functions),
.eint_hw = &mt7629_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mtk_default_register_base_names,
.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
.bias_get = mtk_pinconf_bias_get_rev1,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
};
static const struct of_device_id mt7629_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt7629-pinctrl", },
{}
};
static int mt7629_pinctrl_probe(struct platform_device *pdev)
{
return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
}
static struct platform_driver mt7629_pinctrl_driver = {
.driver = {
.name = "mt7629-pinctrl",
.of_match_table = mt7629_pinctrl_of_match,
},
.probe = mt7629_pinctrl_probe,
};
static int __init mt7629_pinctrl_init(void)
{
return platform_driver_register(&mt7629_pinctrl_driver);
}
arch_initcall(mt7629_pinctrl_init);

2429
drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h Normal file
View file

File diff suppressed because it is too large Load diff

8
drivers/pinctrl/mediatek/pinctrl-paris.c
View file

@ -282,8 +282,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
if (err)
return err;
if (err)
return err;
} else {
return -ENOTSUPP;
}
@ -419,8 +419,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(hw->dev, "missing pins property in node %s .\n",
node->name);
dev_err(hw->dev, "missing pins property in node %pOFn .\n",
node);
return -EINVAL;
}

12
drivers/pinctrl/meson/pinctrl-meson-gxl.c
View file

@ -239,13 +239,9 @@ static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 };
static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 };
static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 };
static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 };
static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 };
static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 };
static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };
static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 };
static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 };
static const unsigned int tsin_a_dp_pins[] = {
GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,
@ -432,10 +428,6 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(spi_miso, 5, 2),
GROUP(spi_ss0, 5, 1),
GROUP(spi_sclk, 5, 0),
GROUP(tsin_a_sop_x, 6, 3),
GROUP(tsin_a_d_valid_x, 6, 2),
GROUP(tsin_a_d0_x, 6, 1),
GROUP(tsin_a_clk_x, 6, 0),
/* Bank Z */
GROUP(eth_mdio, 4, 23),
@ -698,8 +690,8 @@ static const char * const eth_led_groups[] = {
};
static const char * const tsin_a_groups[] = {
"tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x",
"tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x",
"tsin_a_clk", "tsin_a_sop",
"tsin_a_d_valid", "tsin_a_d0",
"tsin_a_dp", "tsin_a_fail",
};

33
drivers/pinctrl/meson/pinctrl-meson8.c
View file

@ -506,6 +506,32 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOZ_12),
GPIO_GROUP(GPIOZ_13),
GPIO_GROUP(GPIOZ_14),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(BOOT_18),
/* bank X */
GROUP(sd_d0_a, 8, 5),
@ -774,7 +800,7 @@ static struct meson_pmx_group meson8_aobus_groups[] = {
GROUP(hdmi_cec_ao, 0, 17),
};
static const char * const gpio_groups[] = {
static const char * const gpio_periphs_groups[] = {
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
@ -807,7 +833,9 @@ static const char * const gpio_groups[] = {
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
@ -994,7 +1022,7 @@ static const char * const hdmi_cec_ao_groups[] = {
};
static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(pcm_a),
@ -1030,6 +1058,7 @@ static struct meson_pmx_func meson8_cbus_functions[] = {
};
static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),

45
drivers/pinctrl/meson/pinctrl-meson8b.c
View file

@ -403,6 +403,34 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
GPIO_GROUP(GPIOH_8),
GPIO_GROUP(GPIOH_9),
GPIO_GROUP(CARD_0),
GPIO_GROUP(CARD_1),
GPIO_GROUP(CARD_2),
GPIO_GROUP(CARD_3),
GPIO_GROUP(CARD_4),
GPIO_GROUP(CARD_5),
GPIO_GROUP(CARD_6),
GPIO_GROUP(BOOT_0),
GPIO_GROUP(BOOT_1),
GPIO_GROUP(BOOT_2),
GPIO_GROUP(BOOT_3),
GPIO_GROUP(BOOT_4),
GPIO_GROUP(BOOT_5),
GPIO_GROUP(BOOT_6),
GPIO_GROUP(BOOT_7),
GPIO_GROUP(BOOT_8),
GPIO_GROUP(BOOT_9),
GPIO_GROUP(BOOT_10),
GPIO_GROUP(BOOT_11),
GPIO_GROUP(BOOT_12),
GPIO_GROUP(BOOT_13),
GPIO_GROUP(BOOT_14),
GPIO_GROUP(BOOT_15),
GPIO_GROUP(BOOT_16),
GPIO_GROUP(BOOT_17),
GPIO_GROUP(BOOT_18),
GPIO_GROUP(DIF_0_P),
GPIO_GROUP(DIF_0_N),
GPIO_GROUP(DIF_1_P),
@ -622,7 +650,7 @@ static struct meson_pmx_group meson8b_aobus_groups[] = {
GROUP(i2s_lr_clk_in, 0, 14),
};
static const char * const gpio_groups[] = {
static const char * const gpio_periphs_groups[] = {
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
"GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
@ -646,16 +674,18 @@ static const char * const gpio_groups[] = {
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
"BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
"GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N",
"DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
"DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
"DIF_4_P", "DIF_4_N"
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
"GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
"GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
"GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
};
static const char * const sd_a_groups[] = {
"sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
"sd_cmd_a"
@ -837,7 +867,7 @@ static const char * const tsin_b_groups[] = {
};
static struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(gpio_periphs),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
FUNCTION(pcm_a),
@ -871,6 +901,7 @@ static struct meson_pmx_func meson8b_cbus_functions[] = {
};
static struct meson_pmx_func meson8b_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_slave_ao),

16
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View file

@ -1799,19 +1799,12 @@ static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
break;
case PIN_CONFIG_INPUT_ENABLE:
if (arg) {
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_IEM,
gpio);
} else
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM,
gpio);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
break;
case PIN_CONFIG_OUTPUT:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM, gpio);
iowrite32(gpio, arg ? bank->base + NPCM7XX_GP_N_DOS :
bank->base + NPCM7XX_GP_N_DOC);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
@ -1932,6 +1925,9 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
pctrl->gpio_bank[id].gc.label =
devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF",
np);
if (pctrl->gpio_bank[id].gc.label == NULL)
return -ENOMEM;
pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
pctrl->gpio_bank[id].direction_input =
pctrl->gpio_bank[id].gc.direction_input;

29
drivers/pinctrl/pinconf.c
View file

@ -366,29 +366,8 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
return 0;
}
static int pinconf_pins_open(struct inode *inode, struct file *file)
{
return single_open(file, pinconf_pins_show, inode->i_private);
}
static int pinconf_groups_open(struct inode *inode, struct file *file)
{
return single_open(file, pinconf_groups_show, inode->i_private);
}
static const struct file_operations pinconf_pins_ops = {
.open = pinconf_pins_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinconf_groups_ops = {
.open = pinconf_groups_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(pinconf_pins);
DEFINE_SHOW_ATTRIBUTE(pinconf_groups);
#define MAX_NAME_LEN 15
@ -613,9 +592,9 @@ void pinconf_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinconf-pins", S_IFREG | S_IRUGO,
devroot, pctldev, &pinconf_pins_ops);
devroot, pctldev, &pinconf_pins_fops);
debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO,
devroot, pctldev, &pinconf_groups_ops);
devroot, pctldev, &pinconf_groups_fops);
debugfs_create_file("pinconf-config", (S_IRUGO | S_IWUSR | S_IWGRP),
devroot, pctldev, &pinconf_dbg_pinconfig_fops);
}

6
drivers/pinctrl/pinctrl-amd.c
View file

@ -791,8 +791,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
static int amd_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
@ -810,8 +809,7 @@ static int amd_gpio_suspend(struct device *dev)
static int amd_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;

6
drivers/pinctrl/pinctrl-at91-pio4.c
View file

@ -868,8 +868,7 @@ static struct pinctrl_desc atmel_pinctrl_desc = {
static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
/*
@ -897,8 +896,7 @@ static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
static int __maybe_unused atmel_pctrl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
for (i = 0; i < atmel_pioctrl->nbanks; i++) {

10
drivers/pinctrl/pinctrl-lpc18xx.c
View file

@ -630,14 +630,8 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = {
LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
};
/**
* enum lpc18xx_pin_config_param - possible pin configuration parameters
* @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt
* controller.
*/
enum lpc18xx_pin_config_param {
PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1,
};
/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params lpc18xx_params[] = {
{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},

14
drivers/pinctrl/pinctrl-max77620.c
View file

@ -34,14 +34,12 @@ enum max77620_pin_ppdrv {
MAX77620_PIN_PP_DRV,
};
enum max77620_pinconf_param {
MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
MAX77620_SUSPEND_FPS_SOURCE,
MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
};
#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
struct max77620_pin_function {
const char *name;

338
drivers/pinctrl/pinctrl-ocelot.c
View file

@ -37,7 +37,6 @@
#define OCELOT_GPIO_ALT1 0x24
#define OCELOT_GPIO_SD_MAP 0x28
#define OCELOT_PINS 22
#define OCELOT_FUNC_PER_PIN 4
enum {
@ -48,6 +47,7 @@ enum {
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
FUNC_MIIM1,
FUNC_MIIM2,
FUNC_PCI_WAKE,
FUNC_PTP0,
FUNC_PTP1,
@ -62,10 +62,23 @@ enum {
FUNC_SFP3,
FUNC_SFP4,
FUNC_SFP5,
FUNC_SFP6,
FUNC_SFP7,
FUNC_SFP8,
FUNC_SFP9,
FUNC_SFP10,
FUNC_SFP11,
FUNC_SFP12,
FUNC_SFP13,
FUNC_SFP14,
FUNC_SFP15,
FUNC_SG0,
FUNC_SG1,
FUNC_SG2,
FUNC_SI,
FUNC_TACHO,
FUNC_TWI,
FUNC_TWI2,
FUNC_TWI_SCL_M,
FUNC_UART,
FUNC_UART2,
@ -80,6 +93,7 @@ static const char *const ocelot_function_names[] = {
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
[FUNC_MIIM1] = "miim1",
[FUNC_MIIM2] = "miim2",
[FUNC_PCI_WAKE] = "pci_wake",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
@ -94,10 +108,23 @@ static const char *const ocelot_function_names[] = {
[FUNC_SFP3] = "sfp3",
[FUNC_SFP4] = "sfp4",
[FUNC_SFP5] = "sfp5",
[FUNC_SFP6] = "sfp6",
[FUNC_SFP7] = "sfp7",
[FUNC_SFP8] = "sfp8",
[FUNC_SFP9] = "sfp9",
[FUNC_SFP10] = "sfp10",
[FUNC_SFP11] = "sfp11",
[FUNC_SFP12] = "sfp12",
[FUNC_SFP13] = "sfp13",
[FUNC_SFP14] = "sfp14",
[FUNC_SFP15] = "sfp15",
[FUNC_SG0] = "sg0",
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
[FUNC_SI] = "si",
[FUNC_TACHO] = "tacho",
[FUNC_TWI] = "twi",
[FUNC_TWI2] = "twi2",
[FUNC_TWI_SCL_M] = "twi_scl_m",
[FUNC_UART] = "uart",
[FUNC_UART2] = "uart2",
@ -118,7 +145,9 @@ struct ocelot_pinctrl {
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct regmap *map;
struct pinctrl_desc *desc;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
};
#define OCELOT_P(p, f0, f1, f2) \
@ -183,6 +212,152 @@ static const struct pinctrl_pin_desc ocelot_pins[] = {
OCELOT_PIN(21),
};
#define JAGUAR2_P(p, f0, f1) \
static struct ocelot_pin_caps jaguar2_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
}, \
}
JAGUAR2_P(0, SG0, NONE);
JAGUAR2_P(1, SG0, NONE);
JAGUAR2_P(2, SG0, NONE);
JAGUAR2_P(3, SG0, NONE);
JAGUAR2_P(4, SG1, NONE);
JAGUAR2_P(5, SG1, NONE);
JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
JAGUAR2_P(8, PTP0, NONE);
JAGUAR2_P(9, PTP1, NONE);
JAGUAR2_P(10, UART, NONE);
JAGUAR2_P(11, UART, NONE);
JAGUAR2_P(12, SG1, NONE);
JAGUAR2_P(13, SG1, NONE);
JAGUAR2_P(14, TWI, TWI_SCL_M);
JAGUAR2_P(15, TWI, NONE);
JAGUAR2_P(16, SI, TWI_SCL_M);
JAGUAR2_P(17, SI, TWI_SCL_M);
JAGUAR2_P(18, SI, TWI_SCL_M);
JAGUAR2_P(19, PCI_WAKE, NONE);
JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
JAGUAR2_P(22, TACHO, NONE);
JAGUAR2_P(23, PWM, NONE);
JAGUAR2_P(24, UART2, NONE);
JAGUAR2_P(25, UART2, SI);
JAGUAR2_P(26, PTP2, SI);
JAGUAR2_P(27, PTP3, SI);
JAGUAR2_P(28, TWI2, SI);
JAGUAR2_P(29, TWI2, SI);
JAGUAR2_P(30, SG2, SI);
JAGUAR2_P(31, SG2, SI);
JAGUAR2_P(32, SG2, SI);
JAGUAR2_P(33, SG2, SI);
JAGUAR2_P(34, NONE, TWI_SCL_M);
JAGUAR2_P(35, NONE, TWI_SCL_M);
JAGUAR2_P(36, NONE, TWI_SCL_M);
JAGUAR2_P(37, NONE, TWI_SCL_M);
JAGUAR2_P(38, NONE, TWI_SCL_M);
JAGUAR2_P(39, NONE, TWI_SCL_M);
JAGUAR2_P(40, NONE, TWI_SCL_M);
JAGUAR2_P(41, NONE, TWI_SCL_M);
JAGUAR2_P(42, NONE, TWI_SCL_M);
JAGUAR2_P(43, NONE, TWI_SCL_M);
JAGUAR2_P(44, NONE, SFP8);
JAGUAR2_P(45, NONE, SFP9);
JAGUAR2_P(46, NONE, SFP10);
JAGUAR2_P(47, NONE, SFP11);
JAGUAR2_P(48, SFP0, NONE);
JAGUAR2_P(49, SFP1, SI);
JAGUAR2_P(50, SFP2, SI);
JAGUAR2_P(51, SFP3, SI);
JAGUAR2_P(52, SFP4, NONE);
JAGUAR2_P(53, SFP5, NONE);
JAGUAR2_P(54, SFP6, NONE);
JAGUAR2_P(55, SFP7, NONE);
JAGUAR2_P(56, MIIM1, SFP12);
JAGUAR2_P(57, MIIM1, SFP13);
JAGUAR2_P(58, MIIM2, SFP14);
JAGUAR2_P(59, MIIM2, SFP15);
JAGUAR2_P(60, NONE, NONE);
JAGUAR2_P(61, NONE, NONE);
JAGUAR2_P(62, NONE, NONE);
JAGUAR2_P(63, NONE, NONE);
#define JAGUAR2_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &jaguar2_pin_##n \
}
static const struct pinctrl_pin_desc jaguar2_pins[] = {
JAGUAR2_PIN(0),
JAGUAR2_PIN(1),
JAGUAR2_PIN(2),
JAGUAR2_PIN(3),
JAGUAR2_PIN(4),
JAGUAR2_PIN(5),
JAGUAR2_PIN(6),
JAGUAR2_PIN(7),
JAGUAR2_PIN(8),
JAGUAR2_PIN(9),
JAGUAR2_PIN(10),
JAGUAR2_PIN(11),
JAGUAR2_PIN(12),
JAGUAR2_PIN(13),
JAGUAR2_PIN(14),
JAGUAR2_PIN(15),
JAGUAR2_PIN(16),
JAGUAR2_PIN(17),
JAGUAR2_PIN(18),
JAGUAR2_PIN(19),
JAGUAR2_PIN(20),
JAGUAR2_PIN(21),
JAGUAR2_PIN(22),
JAGUAR2_PIN(23),
JAGUAR2_PIN(24),
JAGUAR2_PIN(25),
JAGUAR2_PIN(26),
JAGUAR2_PIN(27),
JAGUAR2_PIN(28),
JAGUAR2_PIN(29),
JAGUAR2_PIN(30),
JAGUAR2_PIN(31),
JAGUAR2_PIN(32),
JAGUAR2_PIN(33),
JAGUAR2_PIN(34),
JAGUAR2_PIN(35),
JAGUAR2_PIN(36),
JAGUAR2_PIN(37),
JAGUAR2_PIN(38),
JAGUAR2_PIN(39),
JAGUAR2_PIN(40),
JAGUAR2_PIN(41),
JAGUAR2_PIN(42),
JAGUAR2_PIN(43),
JAGUAR2_PIN(44),
JAGUAR2_PIN(45),
JAGUAR2_PIN(46),
JAGUAR2_PIN(47),
JAGUAR2_PIN(48),
JAGUAR2_PIN(49),
JAGUAR2_PIN(50),
JAGUAR2_PIN(51),
JAGUAR2_PIN(52),
JAGUAR2_PIN(53),
JAGUAR2_PIN(54),
JAGUAR2_PIN(55),
JAGUAR2_PIN(56),
JAGUAR2_PIN(57),
JAGUAR2_PIN(58),
JAGUAR2_PIN(59),
JAGUAR2_PIN(60),
JAGUAR2_PIN(61),
JAGUAR2_PIN(62),
JAGUAR2_PIN(63),
};
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_function_names);
@ -207,9 +382,10 @@ static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
unsigned int pin, unsigned int function)
{
struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
int i;
for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
@ -220,14 +396,17 @@ static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
return -1;
}
#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
unsigned int p = pin->pin % 32;
int f;
f = ocelot_pin_function_idx(group, selector);
f = ocelot_pin_function_idx(info, group, selector);
if (f < 0)
return -EINVAL;
@ -238,10 +417,10 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
*/
regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
f << pin->pin);
regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
f << (pin->pin - 1));
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, pin->pin),
BIT(p), f << p);
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, pin->pin),
BIT(p), f << (p - 1));
return 0;
}
@ -251,9 +430,10 @@ static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned int pin, bool input)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = pin % 32;
regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
input ? 0 : BIT(pin));
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, p), BIT(p),
input ? 0 : BIT(p));
return 0;
}
@ -263,9 +443,12 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
unsigned int offset)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = offset % 32;
regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, offset),
BIT(p), 0);
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, offset),
BIT(p), 0);
return 0;
}
@ -281,13 +464,17 @@ static const struct pinmux_ops ocelot_pmx_ops = {
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_pins);
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->npins;
}
static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return ocelot_pins[group].name;
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->pins[group].name;
}
static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
@ -295,7 +482,9 @@ static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = &ocelot_pins[group].number;
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*pins = &info->desc->pins[group].number;
*num_pins = 1;
return 0;
@ -318,30 +507,47 @@ static struct pinctrl_desc ocelot_desc = {
.owner = THIS_MODULE,
};
static struct pinctrl_desc jaguar2_desc = {
.name = "jaguar2-pinctrl",
.pins = jaguar2_pins,
.npins = ARRAY_SIZE(jaguar2_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
};
static int ocelot_create_group_func_map(struct device *dev,
struct ocelot_pinctrl *info)
{
u16 pins[ARRAY_SIZE(ocelot_pins)];
int f, npins, i;
u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (f = 0; f < FUNC_MAX; f++) {
for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
if (ocelot_pin_function_idx(i, f) >= 0)
for (npins = 0, i = 0; i < info->desc->npins; i++) {
if (ocelot_pin_function_idx(info, i, f) >= 0)
pins[npins++] = i;
}
if (!npins)
continue;
info->func[f].ngroups = npins;
info->func[f].groups = devm_kcalloc(dev,
npins,
sizeof(char *),
GFP_KERNEL);
if (!info->func[f].groups)
info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
GFP_KERNEL);
if (!info->func[f].groups) {
kfree(pins);
return -ENOMEM;
}
for (i = 0; i < npins; i++)
info->func[f].groups[i] = ocelot_pins[pins[i]].name;
info->func[f].groups[i] = info->desc->pins[pins[i]].name;
}
kfree(pins);
return 0;
}
@ -356,7 +562,7 @@ static int ocelot_pinctrl_register(struct platform_device *pdev,
return ret;
}
info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
if (IS_ERR(info->pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(info->pctl);
@ -370,9 +576,9 @@ static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, OCELOT_GPIO_IN, &val);
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
return !!(val & BIT(offset));
return !!(val & BIT(offset % 32));
}
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
@ -381,9 +587,11 @@ static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
if (value)
regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
BIT(offset % 32));
else
regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
BIT(offset % 32));
}
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
@ -392,9 +600,9 @@ static int ocelot_gpio_get_direction(struct gpio_chip *chip,
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, OCELOT_GPIO_OE, &val);
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
return !(val & BIT(offset));
return !(val & BIT(offset % 32));
}
static int ocelot_gpio_direction_input(struct gpio_chip *chip,
@ -407,12 +615,14 @@ static int ocelot_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int pin = BIT(offset);
unsigned int pin = BIT(offset % 32);
if (value)
regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
pin);
else
regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
pin);
return pinctrl_gpio_direction_output(chip->base + offset);
}
@ -434,7 +644,8 @@ static void ocelot_irq_mask(struct irq_data *data)
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio), 0);
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
BIT(gpio % 32), 0);
}
static void ocelot_irq_unmask(struct irq_data *data)
@ -443,8 +654,8 @@ static void ocelot_irq_unmask(struct irq_data *data)
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio),
BIT(gpio));
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
BIT(gpio % 32), BIT(gpio % 32));
}
static void ocelot_irq_ack(struct irq_data *data)
@ -453,7 +664,8 @@ static void ocelot_irq_ack(struct irq_data *data)
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_write_bits(info->map, OCELOT_GPIO_INTR, BIT(gpio), BIT(gpio));
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
BIT(gpio % 32), BIT(gpio % 32));
}
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
@ -497,22 +709,25 @@ static void ocelot_irq_handler(struct irq_desc *desc)
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = 0, irq;
unsigned int reg = 0, irq, i;
unsigned long irqs;
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT, &reg);
if (!reg)
return;
for (i = 0; i < info->stride; i++) {
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, &reg);
if (!reg)
continue;
chained_irq_enter(parent_chip, desc);
chained_irq_enter(parent_chip, desc);
irqs = reg;
irqs = reg;
for_each_set_bit(irq, &irqs, OCELOT_PINS) {
generic_handle_irq(irq_linear_revmap(chip->irq.domain, irq));
for_each_set_bit(irq, &irqs,
min(32U, info->desc->npins - 32 * i))
generic_handle_irq(irq_linear_revmap(chip->irq.domain,
irq + 32 * i));
chained_irq_exit(parent_chip, desc);
}
chained_irq_exit(parent_chip, desc);
}
static int ocelot_gpiochip_register(struct platform_device *pdev,
@ -524,7 +739,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
info->gpio_chip = ocelot_gpiolib_chip;
gc = &info->gpio_chip;
gc->ngpio = OCELOT_PINS;
gc->ngpio = info->desc->npins;
gc->parent = &pdev->dev;
gc->base = 0;
gc->of_node = info->dev->of_node;
@ -549,15 +764,9 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
return 0;
}
static const struct regmap_config ocelot_pinctrl_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x64,
};
static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "mscc,ocelot-pinctrl" },
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
{},
};
@ -567,11 +776,18 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
struct ocelot_pinctrl *info;
void __iomem *base;
int ret;
struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
base = devm_ioremap_resource(dev,
platform_get_resource(pdev, IORESOURCE_MEM, 0));
if (IS_ERR(base)) {
@ -579,8 +795,10 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
return PTR_ERR(base);
}
info->map = devm_regmap_init_mmio(dev, base,
&ocelot_pinctrl_regmap_config);
info->stride = 1 + (info->desc->npins - 1) / 32;
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
info->map = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(info->map)) {
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(info->map);

52
drivers/pinctrl/pinctrl-rockchip.c
View file

@ -307,6 +307,12 @@ struct rockchip_mux_recalced_data {
u8 mask;
};
enum rockchip_mux_route_location {
ROCKCHIP_ROUTE_SAME = 0,
ROCKCHIP_ROUTE_PMU,
ROCKCHIP_ROUTE_GRF,
};
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @bank_num: bank number.
@ -319,6 +325,7 @@ struct rockchip_mux_route_data {
u8 bank_num;
u8 pin;
u8 func;
enum rockchip_mux_route_location route_location;
u32 route_offset;
u32 route_val;
};
@ -815,6 +822,26 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
},
};
static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
{
/* non-iomuxed emmc/flash pins on flash-dqs */
.bank_num = 0,
.pin = 24,
.func = 1,
.route_location = ROCKCHIP_ROUTE_GRF,
.route_offset = 0xa0,
.route_val = BIT(16 + 11),
}, {
/* non-iomuxed emmc/flash pins on emmc-clk */
.bank_num = 0,
.pin = 24,
.func = 2,
.route_location = ROCKCHIP_ROUTE_GRF,
.route_offset = 0xa0,
.route_val = BIT(16 + 11) | BIT(11),
},
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
{
/* pwm0-0 */
@ -1091,7 +1118,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *reg, u32 *value)
int mux, u32 *loc, u32 *reg, u32 *value)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
@ -1108,6 +1135,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
if (i >= ctrl->niomux_routes)
return false;
*loc = data->route_location;
*reg = data->route_offset;
*value = data->route_val;
@ -1210,7 +1238,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, rmask, route_reg, route_val;
u32 data, rmask, route_location, route_reg, route_val;
ret = rockchip_verify_mux(bank, pin, mux);
if (ret < 0)
@ -1247,9 +1275,21 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
&route_val)) {
ret = regmap_write(regmap, route_reg, route_val);
if (rockchip_get_mux_route(bank, pin, mux, &route_location,
&route_reg, &route_val)) {
struct regmap *route_regmap = regmap;
/* handle special locations */
switch (route_location) {
case ROCKCHIP_ROUTE_PMU:
route_regmap = info->regmap_pmu;
break;
case ROCKCHIP_ROUTE_GRF:
route_regmap = info->regmap_base;
break;
}
ret = regmap_write(route_regmap, route_reg, route_val);
if (ret)
return ret;
}
@ -3606,6 +3646,8 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
.iomux_routes = rk3188_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};

5
drivers/pinctrl/pinctrl-rza1.c
View file

@ -1225,6 +1225,9 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
chip->base = -1;
chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
np);
if (!chip->label)
return -ENOMEM;
chip->ngpio = of_args.args[2];
chip->of_node = np;
chip->parent = rza1_pctl->dev;
@ -1326,6 +1329,8 @@ static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
pins[i].number = i;
pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
"P%u-%u", port, pin);
if (!pins[i].name)
return -ENOMEM;
if (i % RZA1_PINS_PER_PORT == 0) {
/*

519
drivers/pinctrl/pinctrl-rza2.c Normal file
View file

@ -0,0 +1,519 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
*
* Copyright (C) 2018 Chris Brandt
*/
/*
* This pin controller/gpio combined driver supports Renesas devices of RZ/A2
* family.
*/
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
#include "core.h"
#include "pinmux.h"
#define DRIVER_NAME "pinctrl-rza2"
#define RZA2_PINS_PER_PORT 8
#define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
#define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
/*
* Use 16 lower bits [15:0] for pin identifier
* Use 16 higher bits [31:16] for pin mux function
*/
#define MUX_PIN_ID_MASK GENMASK(15, 0)
#define MUX_FUNC_MASK GENMASK(31, 16)
#define MUX_FUNC_OFFS 16
#define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
static const char port_names[] = "0123456789ABCDEFGHJKLM";
struct rza2_pinctrl_priv {
struct device *dev;
void __iomem *base;
struct pinctrl_pin_desc *pins;
struct pinctrl_desc desc;
struct pinctrl_dev *pctl;
struct pinctrl_gpio_range gpio_range;
int npins;
};
#define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
#define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
#define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
#define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
#define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
#define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
#define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
#define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
#define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
#define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
#define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
#define RZA2_PDR_INPUT 0x02
#define RZA2_PDR_OUTPUT 0x03
#define RZA2_PDR_MASK 0x03
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
#define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
#define PFS_ISEL BIT(6) /* Interrupt Select */
static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
u8 func)
{
u16 mask16;
u16 reg16;
u8 reg8;
/* Set pin to 'Non-use (Hi-z input protection)' */
reg16 = readw(pfc_base + RZA2_PDR(port));
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
writew(reg16, pfc_base + RZA2_PDR(port));
/* Temporarily switch to GPIO */
reg8 = readb(pfc_base + RZA2_PMR(port));
reg8 &= ~BIT(pin);
writeb(reg8, pfc_base + RZA2_PMR(port));
/* PFS Register Write Protect : OFF */
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
/* Set Pin function (interrupt disabled, ISEL=0) */
writeb(func, pfc_base + RZA2_PFS(port, pin));
/* PFS Register Write Protect : ON */
writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
/* Port Mode : Peripheral module pin functions */
reg8 = readb(pfc_base + RZA2_PMR(port));
reg8 |= BIT(pin);
writeb(reg8, pfc_base + RZA2_PMR(port));
}
static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
u8 dir)
{
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u16 mask16;
u16 reg16;
reg16 = readw(pfc_base + RZA2_PDR(port));
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
if (dir == GPIOF_DIR_IN)
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
else
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
writew(reg16, pfc_base + RZA2_PDR(port));
}
static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u16 reg16;
reg16 = readw(priv->base + RZA2_PDR(port));
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
if (reg16 == RZA2_PDR_OUTPUT)
return GPIOF_DIR_OUT;
if (reg16 == RZA2_PDR_INPUT)
return GPIOF_DIR_IN;
/*
* This GPIO controller has a default Hi-Z state that is not input or
* output, so force the pin to input now.
*/
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
return GPIOF_DIR_IN;
}
static int rza2_chip_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
return 0;
}
static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
}
static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
u8 port = RZA2_PIN_ID_TO_PORT(offset);
u8 pin = RZA2_PIN_ID_TO_PIN(offset);
u8 new_value;
new_value = readb(priv->base + RZA2_PODR(port));
if (value)
new_value |= BIT(pin);
else
new_value &= ~BIT(pin);
writeb(new_value, priv->base + RZA2_PODR(port));
}
static int rza2_chip_direction_output(struct gpio_chip *chip,
unsigned int offset, int val)
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_chip_set(chip, offset, val);
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
return 0;
}
static const char * const rza2_gpio_names[] = {
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
"PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
"PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
"PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7",
"PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7",
"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
/* port I does not exist */
"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
"PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
"PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
"PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
};
static struct gpio_chip chip = {
.names = rza2_gpio_names,
.base = -1,
.get_direction = rza2_chip_get_direction,
.direction_input = rza2_chip_direction_input,
.direction_output = rza2_chip_direction_output,
.get = rza2_chip_get,
.set = rza2_chip_set,
};
static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
{
struct device_node *np = priv->dev->of_node;
struct of_phandle_args of_args;
int ret;
chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
chip.of_node = np;
chip.parent = priv->dev;
chip.ngpio = priv->npins;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
&of_args);
if (ret) {
dev_err(priv->dev, "Unable to parse gpio-ranges\n");
return ret;
}
if ((of_args.args[0] != 0) ||
(of_args.args[1] != 0) ||
(of_args.args[2] != priv->npins)) {
dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
return -EINVAL;
}
priv->gpio_range.id = 0;
priv->gpio_range.pin_base = priv->gpio_range.base = 0;
priv->gpio_range.npins = priv->npins;
priv->gpio_range.name = chip.label;
priv->gpio_range.gc = &chip;
/* Register our gpio chip with gpiolib */
ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
if (ret)
return ret;
/* Register pin range with pinctrl core */
pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
dev_dbg(priv->dev, "Registered gpio controller\n");
return 0;
}
static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
{
struct pinctrl_pin_desc *pins;
unsigned int i;
int ret;
pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
priv->pins = pins;
priv->desc.pins = pins;
priv->desc.npins = priv->npins;
for (i = 0; i < priv->npins; i++) {
pins[i].number = i;
pins[i].name = rza2_gpio_names[i];
}
ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
&priv->pctl);
if (ret) {
dev_err(priv->dev, "pinctrl registration failed\n");
return ret;
}
ret = pinctrl_enable(priv->pctl);
if (ret) {
dev_err(priv->dev, "pinctrl enable failed\n");
return ret;
}
ret = rza2_gpio_register(priv);
if (ret) {
dev_err(priv->dev, "GPIO registration failed\n");
return ret;
}
return 0;
}
/*
* For each DT node, create a single pin mapping. That pin mapping will only
* contain a single group of pins, and that group of pins will only have a
* single function that can be selected.
*/
static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **map,
unsigned int *num_maps)
{
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
unsigned int *pins, *psel_val;
int i, ret, npins, gsel, fsel;
struct property *of_pins;
const char **pin_fn;
/* Find out how many pins to map */
of_pins = of_find_property(np, "pinmux", NULL);
if (!of_pins) {
dev_info(priv->dev, "Missing pinmux property\n");
return -ENOENT;
}
npins = of_pins->length / sizeof(u32);
pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
GFP_KERNEL);
pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
if (!pins || !psel_val || !pin_fn)
return -ENOMEM;
/* Collect pin locations and mux settings from DT properties */
for (i = 0; i < npins; ++i) {
u32 value;
ret = of_property_read_u32_index(np, "pinmux", i, &value);
if (ret)
return ret;
pins[i] = value & MUX_PIN_ID_MASK;
psel_val[i] = MUX_FUNC(value);
}
/* Register a single pin group listing all the pins we read from DT */
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
if (gsel < 0)
return gsel;
/*
* Register a single group function where the 'data' is an array PSEL
* register values read from DT.
*/
pin_fn[0] = np->name;
fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
psel_val);
if (fsel < 0) {
ret = fsel;
goto remove_group;
}
dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
/* Create map where to retrieve function and mux settings from */
*num_maps = 0;
*map = kzalloc(sizeof(**map), GFP_KERNEL);
if (!*map) {
ret = -ENOMEM;
goto remove_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
*num_maps = 1;
return 0;
remove_function:
pinmux_generic_remove_function(pctldev, fsel);
remove_group:
pinctrl_generic_remove_group(pctldev, gsel);
dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
return ret;
}
static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned int num_maps)
{
kfree(map);
}
static const struct pinctrl_ops rza2_pinctrl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = rza2_dt_node_to_map,
.dt_free_map = rza2_dt_free_map,
};
static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
unsigned int group)
{
struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
struct function_desc *func;
unsigned int i, *psel_val;
struct group_desc *grp;
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return -EINVAL;
func = pinmux_generic_get_function(pctldev, selector);
if (!func)
return -EINVAL;
psel_val = func->data;
for (i = 0; i < grp->num_pins; ++i) {
dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
psel_val[i]);
rza2_set_pin_function(
priv->base,
RZA2_PIN_ID_TO_PORT(grp->pins[i]),
RZA2_PIN_ID_TO_PIN(grp->pins[i]),
psel_val[i]);
}
return 0;
}
static const struct pinmux_ops rza2_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = rza2_set_mux,
.strict = true,
};
static int rza2_pinctrl_probe(struct platform_device *pdev)
{
struct rza2_pinctrl_priv *priv;
struct resource *res;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
platform_set_drvdata(pdev, priv);
priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
RZA2_PINS_PER_PORT;
priv->desc.name = DRIVER_NAME;
priv->desc.pctlops = &rza2_pinctrl_ops;
priv->desc.pmxops = &rza2_pinmux_ops;
priv->desc.owner = THIS_MODULE;
ret = rza2_pinctrl_register(priv);
if (ret)
return ret;
dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
return 0;
}
static const struct of_device_id rza2_pinctrl_of_match[] = {
{ .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
{ /* sentinel */ }
};
static struct platform_driver rza2_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = rza2_pinctrl_of_match,
},
.probe = rza2_pinctrl_probe,
};
static int __init rza2_pinctrl_init(void)
{
return platform_driver_register(&rza2_pinctrl_driver);
}
core_initcall(rza2_pinctrl_init);
MODULE_AUTHOR("Chris Brandt <[email protected]>");
MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
MODULE_LICENSE("GPL v2");

4
drivers/pinctrl/pinctrl-rzn1.c
View file

@ -112,7 +112,7 @@ struct rzn1_pinctrl {
struct rzn1_pinctrl_regs __iomem *lev2;
u32 lev1_protect_phys;
u32 lev2_protect_phys;
u32 mdio_func[2];
int mdio_func[2];
struct rzn1_pin_group *groups;
unsigned int ngroups;
@ -810,8 +810,8 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
unsigned int maxgroups = 0;
unsigned int nfuncs = 0;
unsigned int i = 0;
int nfuncs = 0;
int ret;
nfuncs = of_get_child_count(np);

11
drivers/pinctrl/pinctrl-sx150x.c
View file

@ -1166,7 +1166,6 @@ static int sx150x_probe(struct i2c_client *client,
}
/* Register GPIO controller */
pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
pctl->gpio.base = -1;
pctl->gpio.ngpio = pctl->data->npins;
pctl->gpio.get_direction = sx150x_gpio_get_direction;
@ -1180,6 +1179,10 @@ static int sx150x_probe(struct i2c_client *client,
pctl->gpio.of_node = dev->of_node;
#endif
pctl->gpio.can_sleep = true;
pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
if (!pctl->gpio.label)
return -ENOMEM;
/*
* Setting multiple pins is not safe when all pins are not
* handled by the same regmap register. The oscio pin (present
@ -1200,13 +1203,15 @@ static int sx150x_probe(struct i2c_client *client,
/* Add Interrupt support if an irq is specified */
if (client->irq > 0) {
pctl->irq_chip.name = devm_kstrdup(dev, client->name,
GFP_KERNEL);
pctl->irq_chip.irq_mask = sx150x_irq_mask;
pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
pctl->irq_chip.name = devm_kstrdup(dev, client->name,
GFP_KERNEL);
if (!pctl->irq_chip.name)
return -ENOMEM;
pctl->irq.masked = ~0;
pctl->irq.sense = 0;

39
drivers/pinctrl/pinctrl-xway.c
View file

@ -1746,14 +1746,6 @@ static int pinmux_xway_probe(struct platform_device *pdev)
}
xway_pctrl_desc.pins = xway_info.pads;
/* register the gpio chip */
xway_chip.parent = &pdev->dev;
ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to register gpio chip\n");
return ret;
}
/* setup the data needed by pinctrl */
xway_pctrl_desc.name = dev_name(&pdev->dev);
xway_pctrl_desc.npins = xway_chip.ngpio;
@ -1775,10 +1767,33 @@ static int pinmux_xway_probe(struct platform_device *pdev)
return ret;
}
/* finish with registering the gpio range in pinctrl */
xway_gpio_range.npins = xway_chip.ngpio;
xway_gpio_range.base = xway_chip.base;
pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
/* register the gpio chip */
xway_chip.parent = &pdev->dev;
xway_chip.owner = THIS_MODULE;
xway_chip.of_node = pdev->dev.of_node;
ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to register gpio chip\n");
return ret;
}
/*
* For DeviceTree-supported systems, the gpio core checks the
* pinctrl's device node for the "gpio-ranges" property.
* If it is present, it takes care of adding the pin ranges
* for the driver. In this case the driver can skip ahead.
*
* In order to remain compatible with older, existing DeviceTree
* files which don't set the "gpio-ranges" property or systems that
* utilize ACPI the driver has to call gpiochip_add_pin_range().
*/
if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) {
/* finish with registering the gpio range in pinctrl */
xway_gpio_range.npins = xway_chip.ngpio;
xway_gpio_range.base = xway_chip.base;
pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
}
dev_info(&pdev->dev, "Init done\n");
return 0;
}

9
drivers/pinctrl/pinctrl-zynq.c
View file

@ -971,15 +971,12 @@ enum zynq_io_standards {
zynq_iostd_max
};
/**
* enum zynq_pin_config_param - possible pin configuration parameters
* @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
/*
* PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
* this parameter (on a custom format) tells the driver which alternative
* IO standard to use.
*/
enum zynq_pin_config_param {
PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1,
};
#define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params zynq_dt_params[] = {
{"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},

29
drivers/pinctrl/pinmux.c
View file

@ -644,37 +644,16 @@ void pinmux_show_setting(struct seq_file *s,
setting->data.mux.func);
}
static int pinmux_functions_open(struct inode *inode, struct file *file)
{
return single_open(file, pinmux_functions_show, inode->i_private);
}
static int pinmux_pins_open(struct inode *inode, struct file *file)
{
return single_open(file, pinmux_pins_show, inode->i_private);
}
static const struct file_operations pinmux_functions_ops = {
.open = pinmux_functions_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations pinmux_pins_ops = {
.open = pinmux_pins_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(pinmux_functions);
DEFINE_SHOW_ATTRIBUTE(pinmux_pins);
void pinmux_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO,
devroot, pctldev, &pinmux_functions_ops);
devroot, pctldev, &pinmux_functions_fops);
debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO,
devroot, pctldev, &pinmux_pins_ops);
devroot, pctldev, &pinmux_pins_fops);
}
#endif /* CONFIG_DEBUG_FS */

19
drivers/pinctrl/qcom/pinctrl-msm.c
View file

@ -1072,6 +1072,25 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
}
}
static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
{
struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
return pinctrl_force_sleep(pctrl->pctrl);
}
static __maybe_unused int msm_pinctrl_resume(struct device *dev)
{
struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
return pinctrl_force_default(pctrl->pctrl);
}
SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
msm_pinctrl_resume);
EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data)
{

2
drivers/pinctrl/qcom/pinctrl-msm.h
View file

@ -123,6 +123,8 @@ struct msm_pinctrl_soc_data {
unsigned int ntiles;
};
extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data);
int msm_pinctrl_remove(struct platform_device *pdev);

1
drivers/pinctrl/qcom/pinctrl-sdm845.c
View file

@ -1300,6 +1300,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = {
static struct platform_driver sdm845_pinctrl_driver = {
.driver = {
.name = "sdm845-pinctrl",
.pm = &msm_pinctrl_dev_pm_ops,
.of_match_table = sdm845_pinctrl_of_match,
},
.probe = sdm845_pinctrl_probe,

22
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View file

@ -1028,10 +1028,23 @@ static int pmic_gpio_probe(struct platform_device *pdev)
return ret;
}
ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
if (ret) {
dev_err(dev, "failed to add pin range\n");
goto err_range;
/*
* For DeviceTree-supported systems, the gpio core checks the
* pinctrl's device node for the "gpio-ranges" property.
* If it is present, it takes care of adding the pin ranges
* for the driver. In this case the driver can skip ahead.
*
* In order to remain compatible with older, existing DeviceTree
* files which don't set the "gpio-ranges" property or systems that
* utilize ACPI the driver has to call gpiochip_add_pin_range().
*/
if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
npins);
if (ret) {
dev_err(dev, "failed to add pin range\n");
goto err_range;
}
}
return 0;
@ -1055,6 +1068,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */
{ .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
{ .compatible = "qcom,pms405-gpio" }, /* 12 GPIO's, holes on 1 9 10 */
{ .compatible = "qcom,spmi-gpio" }, /* Generic */
{ },
};

23
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
View file

@ -762,12 +762,23 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
return ret;
}
ret = gpiochip_add_pin_range(&pctrl->chip,
dev_name(pctrl->dev),
0, 0, pctrl->chip.ngpio);
if (ret) {
dev_err(pctrl->dev, "failed to add pin range\n");
goto unregister_gpiochip;
/*
* For DeviceTree-supported systems, the gpio core checks the
* pinctrl's device node for the "gpio-ranges" property.
* If it is present, it takes care of adding the pin ranges
* for the driver. In this case the driver can skip ahead.
*
* In order to remain compatible with older, existing DeviceTree
* files which don't set the "gpio-ranges" property or systems that
* utilize ACPI the driver has to call gpiochip_add_pin_range().
*/
if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
0, 0, pctrl->chip.ngpio);
if (ret) {
dev_err(pctrl->dev, "failed to add pin range\n");
goto unregister_gpiochip;
}
}
platform_set_drvdata(pdev, pctrl);

2
drivers/pinctrl/samsung/pinctrl-samsung.c
View file

@ -1071,7 +1071,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
continue;
bank = d->pin_banks;
for (i = 0; i < d->nr_banks; ++i, ++bank) {
if (!strcmp(bank->name, np->name)) {
if (of_node_name_eq(np, bank->name)) {
bank->of_node = np;
break;
}

2
drivers/pinctrl/sh-pfc/core.c
View file

@ -221,7 +221,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
"r_width = %u, f_width = %u\n",
crp->reg, value, field, crp->reg_width, crp->field_width);
crp->reg, value, field, crp->reg_width, hweight32(mask));
mask = ~(mask << pos);
value = value << pos;

3
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View file

@ -1969,7 +1969,7 @@ static const unsigned int gether_gmii_pins[] = {
*/
185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
205, 163, 206, 207,
205, 163, 206, 207, 158,
};
static const unsigned int gether_gmii_mux[] = {
ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
@ -2141,6 +2141,7 @@ static const unsigned int lcd0_data24_1_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,

678
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
View file

@ -10,14 +10,45 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_23(0, fn, sfx), \
PORT_GP_4(0, fn, sfx), \
PORT_GP_1(0, 4, fn, sfx), \
PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(0, 11, fn, sfx), \
PORT_GP_1(0, 12, fn, sfx), \
PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_17(3, fn, sfx), \
PORT_GP_1(3, 27, fn, sfx), \
PORT_GP_1(3, 28, fn, sfx), \
PORT_GP_1(3, 29, fn, sfx), \
PORT_GP_26(4, fn, sfx), \
PORT_GP_14(4, fn, sfx), \
PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(4, 20, fn, sfx), \
PORT_GP_1(4, 21, fn, sfx), \
PORT_GP_1(4, 22, fn, sfx), \
PORT_GP_1(4, 23, fn, sfx), \
PORT_GP_1(4, 24, fn, sfx), \
PORT_GP_1(4, 25, fn, sfx), \
PORT_GP_32(5, fn, sfx)
enum {
@ -1284,6 +1315,229 @@ static const unsigned int du0_disp_pins[] = {
static const unsigned int du0_disp_mux[] = {
DU0_DISP_MARK
};
static const unsigned int du1_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
};
static const unsigned int du1_rgb666_mux[] = {
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
DU1_DR3_MARK, DU1_DR2_MARK,
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
DU1_DG3_MARK, DU1_DG2_MARK,
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
DU1_DB3_MARK, DU1_DB2_MARK,
};
static const unsigned int du1_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
};
static const unsigned int du1_rgb888_mux[] = {
DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
};
static const unsigned int du1_clk0_out_pins[] = {
/* DOTCLKOUT0 */
RCAR_GP_PIN(5, 2),
};
static const unsigned int du1_clk0_out_mux[] = {
DU1_DOTCLKOUT0_MARK
};
static const unsigned int du1_clk1_out_pins[] = {
/* DOTCLKOUT1 */
RCAR_GP_PIN(5, 0),
};
static const unsigned int du1_clk1_out_mux[] = {
DU1_DOTCLKOUT1_MARK
};
static const unsigned int du1_clk_in_pins[] = {
/* DOTCLKIN */
RCAR_GP_PIN(5, 1),
};
static const unsigned int du1_clk_in_mux[] = {
DU1_DOTCLKIN_MARK
};
static const unsigned int du1_sync_pins[] = {
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
};
static const unsigned int du1_sync_mux[] = {
DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
};
static const unsigned int du1_oddf_pins[] = {
/* EXODDF/ODDF/DISP/CDE */
RCAR_GP_PIN(5, 3),
};
static const unsigned int du1_oddf_mux[] = {
DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
};
static const unsigned int du1_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(5, 7),
};
static const unsigned int du1_cde_mux[] = {
DU1_CDE_MARK
};
static const unsigned int du1_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(5, 6),
};
static const unsigned int du1_disp_mux[] = {
DU1_DISP_MARK
};
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
};
static const unsigned int i2c0_a_mux[] = {
SCL0_A_MARK, SDA0_A_MARK,
};
static const unsigned int i2c0_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
};
static const unsigned int i2c0_b_mux[] = {
SCL0_B_MARK, SDA0_B_MARK,
};
static const unsigned int i2c0_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
};
static const unsigned int i2c0_c_mux[] = {
SCL0_C_MARK, SDA0_C_MARK,
};
static const unsigned int i2c0_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
};
static const unsigned int i2c0_d_mux[] = {
SCL0_D_MARK, SDA0_D_MARK,
};
static const unsigned int i2c0_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
};
static const unsigned int i2c0_e_mux[] = {
SCL0_E_MARK, SDA0_E_MARK,
};
/* - I2C1 ------------------------------------------------------------------- */
static const unsigned int i2c1_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
};
static const unsigned int i2c1_a_mux[] = {
SCL1_A_MARK, SDA1_A_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
};
static const unsigned int i2c1_b_mux[] = {
SCL1_B_MARK, SDA1_B_MARK,
};
static const unsigned int i2c1_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
};
static const unsigned int i2c1_c_mux[] = {
SCL1_C_MARK, SDA1_C_MARK,
};
static const unsigned int i2c1_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
};
static const unsigned int i2c1_d_mux[] = {
SCL1_D_MARK, SDA1_D_MARK,
};
static const unsigned int i2c1_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
};
static const unsigned int i2c1_e_mux[] = {
SCL1_E_MARK, SDA1_E_MARK,
};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
};
static const unsigned int i2c2_a_mux[] = {
SCL2_A_MARK, SDA2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int i2c2_b_mux[] = {
SCL2_B_MARK, SDA2_B_MARK,
};
static const unsigned int i2c2_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int i2c2_c_mux[] = {
SCL2_C_MARK, SDA2_C_MARK,
};
static const unsigned int i2c2_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int i2c2_d_mux[] = {
SCL2_D_MARK, SDA2_D_MARK,
};
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_a_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
};
static const unsigned int i2c3_a_mux[] = {
SCL3_A_MARK, SDA3_A_MARK,
};
static const unsigned int i2c3_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
};
static const unsigned int i2c3_b_mux[] = {
SCL3_B_MARK, SDA3_B_MARK,
};
static const unsigned int i2c3_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int i2c3_c_mux[] = {
SCL3_C_MARK, SDA3_C_MARK,
};
static const unsigned int i2c3_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
};
static const unsigned int i2c3_d_mux[] = {
SCL3_D_MARK, SDA3_D_MARK,
};
static const unsigned int i2c3_e_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
};
static const unsigned int i2c3_e_mux[] = {
SCL3_E_MARK, SDA3_E_MARK,
};
/* - I2C4 ------------------------------------------------------------------- */
static const unsigned int i2c4_a_pins[] = {
/* SCL, SDA */
@ -1381,6 +1635,29 @@ static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@ -1619,6 +1896,81 @@ static const unsigned int scif_clk_b_pins[] = {
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 7),
};
static const unsigned int sdhi0_data1_mux[] = {
SD0_DAT0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
};
static const unsigned int sdhi0_data4_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
};
static const unsigned int sdhi0_ctrl_mux[] = {
SD0_CLK_MARK, SD0_CMD_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
RCAR_GP_PIN(0, 11),
};
static const unsigned int sdhi0_cd_mux[] = {
SD0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
RCAR_GP_PIN(0, 12),
};
static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
RCAR_GP_PIN(0, 15),
};
static const unsigned int sdhi1_data1_mux[] = {
MMC0_D0_SDHI1_D0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
};
static const unsigned int sdhi1_data4_mux[] = {
MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
};
static const unsigned int sdhi1_ctrl_mux[] = {
MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
RCAR_GP_PIN(0, 19),
};
static const unsigned int sdhi1_cd_mux[] = {
SD1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
RCAR_GP_PIN(0, 20),
};
static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
@ -1674,6 +2026,146 @@ static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK,
USB1_OVC_MARK,
};
/* - VIN0 ------------------------------------------------------------------- */
static const union vin_data vin0_data_pins = {
.data24 = {
/* B */
RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
},
};
static const union vin_data vin0_data_mux = {
.data24 = {
/* B */
VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G0_MARK, VI0_G1_MARK,
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R0_MARK, VI0_R1_MARK,
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
},
};
static const unsigned int vin0_data18_pins[] = {
/* B */
RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
/* G */
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
/* R */
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
};
static const unsigned int vin0_data18_mux[] = {
/* B */
VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
/* G */
VI0_G2_MARK, VI0_G3_MARK,
VI0_G4_MARK, VI0_G5_MARK,
VI0_G6_MARK, VI0_G7_MARK,
/* R */
VI0_R2_MARK, VI0_R3_MARK,
VI0_R4_MARK, VI0_R5_MARK,
VI0_R6_MARK, VI0_R7_MARK,
};
static const unsigned int vin0_sync_pins[] = {
RCAR_GP_PIN(5, 30), /* HSYNC */
RCAR_GP_PIN(5, 31), /* VSYNC */
};
static const unsigned int vin0_sync_mux[] = {
VI0_HSYNC_N_MARK,
VI0_VSYNC_N_MARK,
};
static const unsigned int vin0_field_pins[] = {
RCAR_GP_PIN(5, 29),
};
static const unsigned int vin0_field_mux[] = {
VI0_FIELD_MARK,
};
static const unsigned int vin0_clkenb_pins[] = {
RCAR_GP_PIN(5, 28),
};
static const unsigned int vin0_clkenb_mux[] = {
VI0_CLKENB_MARK,
};
static const unsigned int vin0_clk_pins[] = {
RCAR_GP_PIN(5, 18),
};
static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
},
};
static const union vin_data vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
VI1_DATA4_MARK, VI1_DATA5_MARK,
VI1_DATA6_MARK, VI1_DATA7_MARK,
VI1_DATA8_MARK, VI1_DATA9_MARK,
VI1_DATA10_MARK, VI1_DATA11_MARK,
},
};
static const unsigned int vin1_sync_pins[] = {
RCAR_GP_PIN(3, 11), /* HSYNC */
RCAR_GP_PIN(3, 12), /* VSYNC */
};
static const unsigned int vin1_sync_mux[] = {
VI1_HSYNC_N_MARK,
VI1_VSYNC_N_MARK,
};
static const unsigned int vin1_field_pins[] = {
RCAR_GP_PIN(3, 10),
};
static const unsigned int vin1_field_mux[] = {
VI1_FIELD_MARK,
};
static const unsigned int vin1_clkenb_pins[] = {
RCAR_GP_PIN(3, 9),
};
static const unsigned int vin1_clkenb_mux[] = {
VI1_CLKENB_MARK,
};
static const unsigned int vin1_clk_pins[] = {
RCAR_GP_PIN(3, 0),
};
static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_col),
@ -1698,6 +2190,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du0_oddf),
SH_PFC_PIN_GROUP(du0_cde),
SH_PFC_PIN_GROUP(du0_disp),
SH_PFC_PIN_GROUP(du1_rgb666),
SH_PFC_PIN_GROUP(du1_rgb888),
SH_PFC_PIN_GROUP(du1_clk0_out),
SH_PFC_PIN_GROUP(du1_clk1_out),
SH_PFC_PIN_GROUP(du1_clk_in),
SH_PFC_PIN_GROUP(du1_sync),
SH_PFC_PIN_GROUP(du1_oddf),
SH_PFC_PIN_GROUP(du1_cde),
SH_PFC_PIN_GROUP(du1_disp),
SH_PFC_PIN_GROUP(i2c0_a),
SH_PFC_PIN_GROUP(i2c0_b),
SH_PFC_PIN_GROUP(i2c0_c),
SH_PFC_PIN_GROUP(i2c0_d),
SH_PFC_PIN_GROUP(i2c0_e),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
SH_PFC_PIN_GROUP(i2c1_d),
SH_PFC_PIN_GROUP(i2c1_e),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c2_c),
SH_PFC_PIN_GROUP(i2c2_d),
SH_PFC_PIN_GROUP(i2c3_a),
SH_PFC_PIN_GROUP(i2c3_b),
SH_PFC_PIN_GROUP(i2c3_c),
SH_PFC_PIN_GROUP(i2c3_d),
SH_PFC_PIN_GROUP(i2c3_e),
SH_PFC_PIN_GROUP(i2c4_a),
SH_PFC_PIN_GROUP(i2c4_b),
SH_PFC_PIN_GROUP(i2c4_c),
@ -1710,6 +2230,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@ -1743,6 +2266,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_f),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
@ -1750,6 +2283,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi2_wp),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
SH_PFC_PIN_GROUP(vin0_data18),
VIN_DATA_PIN_GROUP(vin0_data, 16),
VIN_DATA_PIN_GROUP(vin0_data, 12),
VIN_DATA_PIN_GROUP(vin0_data, 10),
VIN_DATA_PIN_GROUP(vin0_data, 8),
SH_PFC_PIN_GROUP(vin0_sync),
SH_PFC_PIN_GROUP(vin0_field),
SH_PFC_PIN_GROUP(vin0_clkenb),
SH_PFC_PIN_GROUP(vin0_clk),
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),
SH_PFC_PIN_GROUP(vin1_clk),
};
static const char * const avb_groups[] = {
@ -1780,6 +2331,49 @@ static const char * const du0_groups[] = {
"du0_disp",
};
static const char * const du1_groups[] = {
"du1_rgb666",
"du1_rgb888",
"du1_clk0_out",
"du1_clk1_out",
"du1_clk_in",
"du1_sync",
"du1_oddf",
"du1_cde",
"du1_disp",
};
static const char * const i2c0_groups[] = {
"i2c0_a",
"i2c0_b",
"i2c0_c",
"i2c0_d",
"i2c0_e",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
"i2c1_c",
"i2c1_d",
"i2c1_e",
};
static const char * const i2c2_groups[] = {
"i2c2_a",
"i2c2_b",
"i2c2_c",
"i2c2_d",
};
static const char * const i2c3_groups[] = {
"i2c3_a",
"i2c3_b",
"i2c3_c",
"i2c3_d",
"i2c3_e",
};
static const char * const i2c4_groups[] = {
"i2c4_a",
"i2c4_b",
@ -1801,6 +2395,12 @@ static const char * const qspi0_groups[] = {
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_data_b",
@ -1855,6 +2455,22 @@ static const char * const scif_clk_groups[] = {
"scif_clk_b",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
@ -1871,12 +2487,42 @@ static const char * const usb1_groups[] = {
"usb1",
};
static const char * const vin0_groups[] = {
"vin0_data24",
"vin0_data20",
"vin0_data18",
"vin0_data16",
"vin0_data12",
"vin0_data10",
"vin0_data8",
"vin0_sync",
"vin0_field",
"vin0_clkenb",
"vin0_clk",
};
static const char * const vin1_groups[] = {
"vin1_data12",
"vin1_data10",
"vin1_data8",
"vin1_sync",
"vin1_field",
"vin1_clkenb",
"vin1_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
@ -1884,9 +2530,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),
SH_PFC_FUNCTION(vin1),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@ -2729,9 +3379,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
u32 *pocctrl)
{
int bit = -EINVAL;
*pocctrl = 0xe60600b0;
if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
bit = 0;
if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
bit = 2;
if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
bit = 1;
return bit;
}
static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
};
#ifdef CONFIG_PINCTRL_PFC_R8A77470
const struct sh_pfc_soc_info r8a77470_pinmux_info = {
.name = "r8a77470_pfc",
.ops = &r8a77470_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },

6
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View file

@ -3217,8 +3217,7 @@ static const unsigned int qspi_data4_b_pins[] = {
RCAR_GP_PIN(6, 4),
};
static const unsigned int qspi_data4_b_mux[] = {
SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
@ -4372,17 +4371,14 @@ static const unsigned int vin1_b_data18_pins[] = {
};
static const unsigned int vin1_b_data18_mux[] = {
/* B */
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
/* G */
VI1_G0_B_MARK, VI1_G1_B_MARK,
VI1_G2_B_MARK, VI1_G3_B_MARK,
VI1_G4_B_MARK, VI1_G5_B_MARK,
VI1_G6_B_MARK, VI1_G7_B_MARK,
/* R */
VI1_R0_B_MARK, VI1_R1_B_MARK,
VI1_R2_B_MARK, VI1_R3_B_MARK,
VI1_R4_B_MARK, VI1_R5_B_MARK,
VI1_R6_B_MARK, VI1_R7_B_MARK,

22
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
View file

@ -1474,7 +1474,7 @@ static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
/* - VIN2 ------------------------------------------------------------------- */
static const union vin_data vin2_data_pins = {
static const union vin_data16 vin2_data_pins = {
.data16 = {
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
@ -1486,7 +1486,7 @@ static const union vin_data vin2_data_pins = {
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
},
};
static const union vin_data vin2_data_mux = {
static const union vin_data16 vin2_data_mux = {
.data16 = {
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
@ -1524,7 +1524,7 @@ static const unsigned int vin2_clk_mux[] = {
VI2_CLK_MARK,
};
/* - VIN3 ------------------------------------------------------------------- */
static const union vin_data vin3_data_pins = {
static const union vin_data16 vin3_data_pins = {
.data16 = {
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
@ -1536,7 +1536,7 @@ static const union vin_data vin3_data_pins = {
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
},
};
static const union vin_data vin3_data_mux = {
static const union vin_data16 vin3_data_mux = {
.data16 = {
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
@ -1574,7 +1574,7 @@ static const unsigned int vin3_clk_mux[] = {
VI3_CLK_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const union vin_data vin4_data_pins = {
static const union vin_data12 vin4_data_pins = {
.data12 = {
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
@ -1584,7 +1584,7 @@ static const union vin_data vin4_data_pins = {
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
},
};
static const union vin_data vin4_data_mux = {
static const union vin_data12 vin4_data_mux = {
.data12 = {
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
@ -1620,7 +1620,7 @@ static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data vin5_data_pins = {
static const union vin_data12 vin5_data_pins = {
.data12 = {
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
@ -1630,7 +1630,7 @@ static const union vin_data vin5_data_pins = {
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
},
};
static const union vin_data vin5_data_mux = {
static const union vin_data12 vin5_data_mux = {
.data12 = {
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
@ -1744,10 +1744,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
VIN_DATA_PIN_GROUP(vin1_data, 12),
VIN_DATA_PIN_GROUP(vin1_data, 10),
VIN_DATA_PIN_GROUP(vin1_data, 8),
VIN_DATA_PIN_GROUP(vin1_data_b, 24),
VIN_DATA_PIN_GROUP(vin1_data_b, 20),
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
SH_PFC_PIN_GROUP(vin1_data18_b),
VIN_DATA_PIN_GROUP(vin1_data_b, 16),
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
SH_PFC_PIN_GROUP(vin1_sync),
SH_PFC_PIN_GROUP(vin1_field),
SH_PFC_PIN_GROUP(vin1_clkenb),

6
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View file

@ -3704,7 +3704,7 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ------------------------------------------------------------------- */
static const union vin_data vin1_data_pins = {
static const union vin_data12 vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
@ -3714,7 +3714,7 @@ static const union vin_data vin1_data_pins = {
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
},
};
static const union vin_data vin1_data_mux = {
static const union vin_data12 vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
@ -5212,7 +5212,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
/* IP9_31 [1] */
0, 0,
/* IP9_30_28 [3] */

97
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
View file

@ -537,6 +537,9 @@ MOD_SEL0_2_1 MOD_SEL1_2 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
@ -562,6 +565,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@ -574,9 +578,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
PINMUX_SINGLE(I2C_SEL_0_1),
PINMUX_SINGLE(I2C_SEL_3_1),
PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -608,13 +609,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@ -664,16 +667,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
PINMUX_IPSR_GPSR(IP1_23_20, A21),
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
PINMUX_IPSR_GPSR(IP1_27_24, A20),
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@ -1067,11 +1072,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
@ -2266,6 +2273,15 @@ static const unsigned int hscif4_data_b_mux[] = {
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
@ -2294,6 +2310,25 @@ static const unsigned int i2c2_b_pins[] = {
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
@ -3936,10 +3971,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@ -4309,6 +4347,10 @@ static const char * const hscif4_groups[] = {
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@ -4319,6 +4361,14 @@ static const char * const i2c2_groups[] = {
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@ -4651,8 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),

119
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View file

@ -550,6 +550,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
@ -575,6 +578,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@ -588,9 +592,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
PINMUX_SINGLE(I2C_SEL_0_1),
PINMUX_SINGLE(I2C_SEL_3_1),
PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -614,14 +615,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@ -674,14 +677,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@ -1113,11 +1118,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
@ -2348,6 +2355,15 @@ static const unsigned int hscif4_data_b_mux[] = {
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
@ -2376,6 +2392,25 @@ static const unsigned int i2c2_b_pins[] = {
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
@ -4258,10 +4293,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@ -4474,20 +4512,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb2),
SH_PFC_PIN_GROUP(usb2_ch3),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@ -4662,6 +4700,10 @@ static const char * const hscif4_groups[] = {
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@ -4672,6 +4714,14 @@ static const char * const i2c2_groups[] = {
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@ -5032,8 +5082,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),

122
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View file

@ -556,6 +556,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
@ -581,6 +584,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@ -617,13 +621,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@ -675,14 +681,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@ -1115,13 +1123,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
@ -2347,6 +2357,15 @@ static const unsigned int hscif4_data_b_mux[] = {
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
@ -2375,6 +2394,25 @@ static const unsigned int i2c2_b_pins[] = {
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
@ -4124,7 +4162,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[307];
struct sh_pfc_pin_group common[310];
struct sh_pfc_pin_group automotive[33];
} pinmux_groups = {
.common = {
@ -4197,10 +4235,13 @@ static const struct {
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@ -4409,20 +4450,20 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@ -4629,6 +4670,10 @@ static const char * const hscif4_groups[] = {
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@ -4639,6 +4684,14 @@ static const char * const i2c2_groups[] = {
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@ -4967,7 +5020,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
struct sh_pfc_function common[45];
struct sh_pfc_function common[48];
struct sh_pfc_function automotive[6];
} pinmux_functions = {
.common = {
@ -4983,8 +5036,11 @@ static const struct {
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),

370
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
View file

@ -1784,6 +1784,72 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
AVB_AVTP_CAPTURE_B_MARK,
};
/* - CAN ------------------------------------------------------------------ */
static const unsigned int can0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int can0_data_a_mux[] = {
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int can1_data_mux[] = {
CAN1_TX_MARK, CAN1_RX_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 25),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - CAN FD --------------------------------------------------------------- */
static const unsigned int canfd0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int canfd0_data_a_mux[] = {
CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
};
static const unsigned int canfd0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
};
static const unsigned int canfd0_data_b_mux[] = {
CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
};
static const unsigned int canfd1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
@ -3725,6 +3791,216 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_a_pins[] = {
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_a_mux[] = {
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_a_pins = {
.data24 = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_a_mux = {
.data24 = {
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_data18_b_pins[] = {
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_b_pins = {
.data24 = {
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
},
};
static const union vin_data vin4_data_b_mux = {
.data24 = {
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
RCAR_GP_PIN(1, 16),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
RCAR_GP_PIN(1, 19),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
RCAR_GP_PIN(1, 27),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ------------------------------------------------------------------- */
static const union vin_data16 vin5_data_pins = {
.data16 = {
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
},
};
static const union vin_data16 vin5_data_mux = {
.data16 = {
VI5_DATA0_MARK, VI5_DATA1_MARK,
VI5_DATA2_MARK, VI5_DATA3_MARK,
VI5_DATA4_MARK, VI5_DATA5_MARK,
VI5_DATA6_MARK, VI5_DATA7_MARK,
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
static const unsigned int vin5_sync_pins[] = {
/* VSYNC_N, HSYNC_N */
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
};
static const unsigned int vin5_sync_mux[] = {
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
};
static const unsigned int vin5_field_pins[] = {
RCAR_GP_PIN(1, 11),
};
static const unsigned int vin5_field_mux[] = {
VI5_FIELD_MARK,
};
static const unsigned int vin5_clkenb_pins[] = {
RCAR_GP_PIN(1, 20),
};
static const unsigned int vin5_clkenb_mux[] = {
VI5_CLKENB_MARK,
};
static const unsigned int vin5_clk_pins[] = {
RCAR_GP_PIN(1, 21),
};
static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@ -3754,6 +4030,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
@ -4000,6 +4283,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
VIN_DATA_PIN_GROUP(vin5_data, 8),
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
};
static const char * const audio_clk_groups[] = {
@ -4036,6 +4345,28 @@ static const char * const avb_groups[] = {
"avb_avtp_capture_b",
};
static const char * const can0_groups[] = {
"can0_data_a",
"can0_data_b",
};
static const char * const can1_groups[] = {
"can1_data",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const canfd0_groups[] = {
"canfd0_data_a",
"canfd0_data_b",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
@ -4392,9 +4723,46 @@ static const char * const usb30_groups[] = {
"usb30",
};
static const char * const vin4_groups[] = {
"vin4_data8_a",
"vin4_data10_a",
"vin4_data12_a",
"vin4_data16_a",
"vin4_data18_a",
"vin4_data20_a",
"vin4_data24_a",
"vin4_data8_b",
"vin4_data10_b",
"vin4_data12_b",
"vin4_data16_b",
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const char * const vin5_groups[] = {
"vin5_data8",
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
"vin5_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
@ -4432,6 +4800,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

72
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
View file

@ -1382,6 +1382,56 @@ static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - SCIF Clock ------------------------------------------------------------- */
static const unsigned int scif_clk_a_pins[] = {
/* SCIF_CLK */
@ -1756,6 +1806,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif0_data),
@ -1950,6 +2006,18 @@ static const char * const pwm4_groups[] = {
"pwm4_b",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif_clk_groups[] = {
"scif_clk_a",
"scif_clk_b",
@ -2033,6 +2101,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
@ -2351,7 +2421,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4, 4, 4, 4,
4, 4, 4, 4, 4,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

72
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
View file

@ -1660,6 +1660,56 @@ static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
};
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
static const unsigned int qspi0_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
};
static const unsigned int qspi0_data4_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK
};
/* - QSPI1 ------------------------------------------------------------------ */
static const unsigned int qspi1_ctrl_pins[] = {
/* SPCLK, SSL */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
};
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
static const unsigned int qspi1_data2_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
};
static const unsigned int qspi1_data4_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@ -2092,6 +2142,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2),
SH_PFC_PIN_GROUP(qspi0_data4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2),
SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@ -2316,6 +2372,18 @@ static const char * const pwm4_groups[] = {
"pwm4_b",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
"qspi0_data4",
};
static const char * const qspi1_groups[] = {
"qspi1_ctrl",
"qspi1_data2",
"qspi1_data4",
};
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@ -2412,6 +2480,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
@ -2751,7 +2821,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4, 4, 4, 4,
4, 4, 4, 4, 4,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

1466
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
View file

File diff suppressed because it is too large Load diff

14
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
View file

@ -388,10 +388,10 @@ FM(IP12_31_28) IP12_31_28 \
#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) F_(0, 0)
#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) F_(0, 0)
#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0)
#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0)
#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
@ -468,12 +468,6 @@ enum {
#undef FM
};
#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##msel)
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),

9
drivers/pinctrl/sh-pfc/pfc-sh7264.c
View file

@ -1713,6 +1713,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF12MD_000, PF12MD_001, 0, PF12MD_011,
PF12MD_100, PF12MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
@ -1756,8 +1759,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
PF1MD_100, PF1MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
}
0, 0, 0, 0, 0, 0, 0, 0,
PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
PF0MD_100, PF0MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {

2
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View file

@ -2116,7 +2116,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC8_IN, PC8_OUT,
PC7_IN, PC7_OUT,
PC6_IN, PC6_OUT,

1
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View file

@ -3073,6 +3073,7 @@ static const unsigned int tpu4_to2_mux[] = {
};
static const unsigned int tpu4_to3_pins[] = {
/* TO */
PIN_NUMBER(6, 26),
};
static const unsigned int tpu4_to3_mux[] = {
TPU4TO3_MARK,

20
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View file

@ -2210,31 +2210,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP10_22 [1] */
FN_CAN_CLK_A, FN_RX4_D,
/* IP10_21_19 [3] */
FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B,
FN_LCD_M_DISP_B, 0, 0, 0,
FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
FN_LCD_M_DISP_B, 0, 0,
/* IP10_18_16 [3] */
FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B,
FN_LCD_VEPWC_B, 0, 0, 0,
FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
FN_LCD_VEPWC_B, 0, 0,
/* IP10_15 [1] */
FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
/* IP10_14_12 [3] */
FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
FN_LCD_FLM_B, 0, 0, 0,
/* IP10_11_9 [3] */
FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B,
FN_LCD_CL2_B, 0, 0, 0,
FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
FN_LCD_CL2_B, 0, 0,
/* IP10_8_6 [3] */
FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B,
FN_LCD_CL1_B, 0, 0, 0,
FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
FN_LCD_CL1_B, 0, 0,
/* IP10_5_3 [3] */
FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
FN_LCD_DON_B, 0, 0, 0,
FN_LCD_DON_B, 0, 0,
/* IP10_2_0 [3] */
FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
FN_LCD_DATA15_B, 0, 0, 0 }
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
/* IP11_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_28 [1] */

60
drivers/pinctrl/sh-pfc/sh_pfc.h
View file

@ -41,7 +41,8 @@ struct sh_pfc_pin {
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
.nr_pins = ARRAY_SIZE(n##_pins) + \
BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
@ -53,18 +54,32 @@ struct sh_pfc_pin_group {
};
/*
* Using union vin_data saves memory occupied by the VIN data pins.
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
* in this case.
* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
* in this case. It accepts an optional 'version' argument used when the
* same group can appear on a different set of pins.
*/
#define VIN_DATA_PIN_GROUP(n, s) \
{ \
.name = #n#s, \
.pins = n##_pins.data##s, \
.mux = n##_mux.data##s, \
.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
#define VIN_DATA_PIN_GROUP(n, s, ...) \
{ \
.name = #n#s#__VA_ARGS__, \
.pins = n##__VA_ARGS__##_pins.data##s, \
.mux = n##__VA_ARGS__##_mux.data##s, \
.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
}
union vin_data12 {
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
};
union vin_data16 {
unsigned int data16[16];
unsigned int data12[12];
unsigned int data10[10];
unsigned int data8[8];
};
union vin_data {
unsigned int data24[24];
unsigned int data20[20];
@ -127,8 +142,7 @@ struct pinmux_cfg_reg {
*/
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 [r_width]) \
{ var_fw0, var_fwn, 0 }, \
.var_field_width = (const u8 []) { var_fw0, var_fwn, 0 }, \
.enum_ids = (const u16 [])
struct pinmux_drive_reg_field {
@ -372,6 +386,28 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
/*
* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
* an additional select register that controls physical multiplexing
* with another pin.
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
* - psel: Physical multiplexing selector
* - msel: Module selector
*/
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
/*
* Describe a pinmux configuration in which a pin is physically multiplexed
* with other pins.
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
* - psel: Physical multiplexing selector
*/
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
PINMUX_DATA(fn##_MARK, FN_##psel)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
* capability.

6
drivers/pinctrl/sprd/pinctrl-sprd.c
View file

@ -159,10 +159,8 @@ struct sprd_pinctrl {
struct sprd_pinctrl_soc_info *info;
};
enum sprd_pinconf_params {
SPRD_PIN_CONFIG_CONTROL = PIN_CONFIG_END + 1,
SPRD_PIN_CONFIG_SLEEP_MODE = PIN_CONFIG_END + 2,
};
#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
#define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
const char *name)

71
drivers/pinctrl/stm32/pinctrl-stm32.c
View file

@ -8,6 +8,7 @@
*/
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/hwspinlock.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
@ -51,6 +52,8 @@
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
#define HWSPINLOCK_TIMEOUT 5 /* msec */
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
@ -91,6 +94,7 @@ struct stm32_pinctrl {
struct irq_domain *domain;
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
struct hwspinlock *hwlock;
};
static inline int stm32_gpio_pin(int gpio)
@ -576,14 +580,24 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock)
err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
@ -594,6 +608,10 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
if (pctl->hwlock)
hwspin_unlock(pctl->hwlock);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@ -683,17 +701,31 @@ static const struct pinmux_ops stm32_pmx_ops = {
static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock)
err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
if (pctl->hwlock)
hwspin_unlock(pctl->hwlock);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@ -719,17 +751,31 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock)
err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
if (pctl->hwlock)
hwspin_unlock(pctl->hwlock);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@ -755,17 +801,31 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock)
err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
if (err) {
dev_err(pctl->dev, "Can't get hwspinlock\n");
goto unlock;
}
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= bias << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
if (pctl->hwlock)
hwspin_unlock(pctl->hwlock);
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@ -1140,7 +1200,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct stm32_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
int i, ret, banks = 0;
int i, ret, hwlock_id, banks = 0;
if (!np)
return -EINVAL;
@ -1160,6 +1220,15 @@ int stm32_pctl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pctl);
/* hwspinlock is optional */
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
if (hwlock_id < 0) {
if (hwlock_id == -EPROBE_DEFER)
return hwlock_id;
} else {
pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
}
pctl->dev = dev;
pctl->match_data = match->data;
ret = stm32_pctrl_build_state(pdev);

4
drivers/pinctrl/sunxi/Kconfig
View file

@ -6,6 +6,10 @@ config PINCTRL_SUNXI
select GENERIC_PINCONF
select GPIOLIB
config PINCTRL_SUNIV_F1C100S
def_bool MACH_SUNIV
select PINCTRL_SUNXI
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI

1
drivers/pinctrl/sunxi/Makefile
View file

@ -3,6 +3,7 @@
obj-y += pinctrl-sunxi.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o
obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o
obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o

52
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
View file

@ -323,71 +323,71 @@ static const struct sunxi_desc_pin a64_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* PCK */
SUNXI_FUNCTION(0x4, "ts0")), /* CLK */
SUNXI_FUNCTION(0x2, "csi"), /* PCK */
SUNXI_FUNCTION(0x4, "ts")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* CK */
SUNXI_FUNCTION(0x4, "ts0")), /* ERR */
SUNXI_FUNCTION(0x2, "csi"), /* CK */
SUNXI_FUNCTION(0x4, "ts")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */
SUNXI_FUNCTION(0x4, "ts0")), /* SYNC */
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x4, "ts")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */
SUNXI_FUNCTION(0x4, "ts0")), /* DVLD */
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x4, "ts")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D0 */
SUNXI_FUNCTION(0x4, "ts0")), /* D0 */
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x4, "ts")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D1 */
SUNXI_FUNCTION(0x4, "ts0")), /* D1 */
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x4, "ts")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D2 */
SUNXI_FUNCTION(0x4, "ts0")), /* D2 */
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x4, "ts")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D3 */
SUNXI_FUNCTION(0x4, "ts0")), /* D3 */
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x4, "ts")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D4 */
SUNXI_FUNCTION(0x4, "ts0")), /* D4 */
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x4, "ts")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D5 */
SUNXI_FUNCTION(0x4, "ts0")), /* D5 */
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x4, "ts")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D6 */
SUNXI_FUNCTION(0x4, "ts0")), /* D6 */
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x4, "ts")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D7 */
SUNXI_FUNCTION(0x4, "ts0")), /* D7 */
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x4, "ts")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0")), /* SCK */
SUNXI_FUNCTION(0x2, "csi")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0")), /* SDA */
SUNXI_FUNCTION(0x2, "csi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),

416
drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c Normal file
View file

@ -0,0 +1,416 @@
/*
* Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
*
* Copyright (C) 2018 Icenowy Zheng
*
* Icenowy Zheng <icenowy@aosc.io>
*
* Copyright (C) 2014 Jackie Hwang
*
* Jackie Hwang <huangshr@allwinnertech.com>
*
* Copyright (C) 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
SUNXI_FUNCTION(0x6, "spi1")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* CKE */
SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION(0x5, "uart1"), /* RX */
SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
SUNXI_FUNCTION(0x3, "ir0"), /* RX */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "uart1"), /* TX */
SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS */
SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
SUNXI_FUNCTION(0x3, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
SUNXI_FUNCTION(0x3, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
SUNXI_FUNCTION(0x3, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
SUNXI_FUNCTION(0x3, "spi0"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
SUNXI_FUNCTION(0x5, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
SUNXI_FUNCTION(0x5, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
SUNXI_FUNCTION(0x4, "clk"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
SUNXI_FUNCTION(0x4, "i2s"), /* IN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
SUNXI_FUNCTION(0x4, "ir"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
SUNXI_FUNCTION(0x4, "ir0"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
};
static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
.pins = suniv_f1c100s_pins,
.npins = ARRAY_SIZE(suniv_f1c100s_pins),
.irq_banks = 3,
};
static int suniv_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&suniv_f1c100s_pinctrl_data);
}
static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
{ .compatible = "allwinner,suniv-f1c100s-pinctrl", },
{}
};
static struct platform_driver suniv_f1c100s_pinctrl_driver = {
.probe = suniv_pinctrl_probe,
.driver = {
.name = "suniv-f1c100s-pinctrl",
.of_match_table = suniv_f1c100s_pinctrl_match,
},
};
builtin_platform_driver(suniv_f1c100s_pinctrl_driver);

63
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View file

@ -26,6 +26,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/regulator/consumer.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@ -693,12 +694,74 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned short bank = offset / PINS_PER_BANK;
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank];
struct regulator *reg;
int ret;
reg = s_reg->regulator;
if (!reg) {
char supply[16];
snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
reg = regulator_get(pctl->dev, supply);
if (IS_ERR(reg)) {
dev_err(pctl->dev, "Couldn't get bank P%c regulator\n",
'A' + bank);
return PTR_ERR(reg);
}
s_reg->regulator = reg;
refcount_set(&s_reg->refcount, 1);
} else {
refcount_inc(&s_reg->refcount);
}
ret = regulator_enable(reg);
if (ret) {
dev_err(pctl->dev,
"Couldn't enable bank P%c regulator\n", 'A' + bank);
goto out;
}
return 0;
out:
if (refcount_dec_and_test(&s_reg->refcount)) {
regulator_put(s_reg->regulator);
s_reg->regulator = NULL;
}
return ret;
}
static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
unsigned short bank = offset / PINS_PER_BANK;
struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank];
if (!refcount_dec_and_test(&s_reg->refcount))
return 0;
regulator_disable(s_reg->regulator);
regulator_put(s_reg->regulator);
s_reg->regulator = NULL;
return 0;
}
static const struct pinmux_ops sunxi_pmx_ops = {
.get_functions_count = sunxi_pmx_get_funcs_cnt,
.get_function_name = sunxi_pmx_get_func_name,
.get_function_groups = sunxi_pmx_get_func_groups,
.set_mux = sunxi_pmx_set_mux,
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
.request = sunxi_pmx_request,
.free = sunxi_pmx_free,
.strict = true,
};

6
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View file

@ -126,11 +126,17 @@ struct sunxi_pinctrl_group {
unsigned pin;
};
struct sunxi_pinctrl_regulator {
struct regulator *regulator;
refcount_t refcount;
};
struct sunxi_pinctrl {
void __iomem *membase;
struct gpio_chip *chip;
const struct sunxi_pinctrl_desc *desc;
struct device *dev;
struct sunxi_pinctrl_regulator regulators[12];
struct irq_domain *domain;
struct sunxi_pinctrl_function *functions;
unsigned nfunctions;

22
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/list.h>
#include <linux/mfd/syscon.h>
@ -46,7 +36,7 @@ struct uniphier_pinctrl_priv {
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct regmap *regmap;
struct uniphier_pinctrl_socdata *socdata;
const struct uniphier_pinctrl_socdata *socdata;
struct list_head reg_regions;
};
@ -869,7 +859,7 @@ const struct dev_pm_ops uniphier_pinctrl_pm_ops = {
};
int uniphier_pinctrl_probe(struct platform_device *pdev,
struct uniphier_pinctrl_socdata *socdata)
const struct uniphier_pinctrl_socdata *socdata)
{
struct device *dev = &pdev->dev;
struct uniphier_pinctrl_priv *priv;

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2016-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -690,7 +680,7 @@ static int uniphier_ld11_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_ld11_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_ld11_pindata = {
.pins = uniphier_ld11_pins,
.npins = ARRAY_SIZE(uniphier_ld11_pins),
.groups = uniphier_ld11_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2016-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -795,7 +785,7 @@ static int uniphier_ld20_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_ld20_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_ld20_pindata = {
.pins = uniphier_ld20_pins,
.npins = ARRAY_SIZE(uniphier_ld20_pins),
.groups = uniphier_ld20_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -723,7 +713,7 @@ static int uniphier_ld4_get_gpio_muxval(unsigned int pin,
}
}
static struct uniphier_pinctrl_socdata uniphier_ld4_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_ld4_pindata = {
.pins = uniphier_ld4_pins,
.npins = ARRAY_SIZE(uniphier_ld4_pins),
.groups = uniphier_ld4_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -938,7 +928,7 @@ static int uniphier_ld6b_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_ld6b_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_ld6b_pindata = {
.pins = uniphier_ld6b_pins,
.npins = ARRAY_SIZE(uniphier_ld6b_pins),
.groups = uniphier_ld6b_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program5 is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -1232,7 +1222,7 @@ static int uniphier_pro4_get_gpio_muxval(unsigned int pin,
return 7;
}
static struct uniphier_pinctrl_socdata uniphier_pro4_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_pro4_pindata = {
.pins = uniphier_pro4_pins,
.npins = ARRAY_SIZE(uniphier_pro4_pins),
.groups = uniphier_pro4_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program5 is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -996,7 +986,7 @@ static int uniphier_pro5_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_pro5_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_pro5_pindata = {
.pins = uniphier_pro5_pins,
.npins = ARRAY_SIZE(uniphier_pro5_pins),
.groups = uniphier_pro5_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -960,7 +950,7 @@ static int uniphier_pxs2_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_pxs2_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_pxs2_pindata = {
.pins = uniphier_pxs2_pins,
.npins = ARRAY_SIZE(uniphier_pxs2_pins),
.groups = uniphier_pxs2_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/init.h>
#include <linux/kernel.h>
@ -971,7 +961,7 @@ static int uniphier_pxs3_get_gpio_muxval(unsigned int pin,
return 15;
}
static struct uniphier_pinctrl_socdata uniphier_pxs3_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_pxs3_pindata = {
.pins = uniphier_pxs3_pins,
.npins = ARRAY_SIZE(uniphier_pxs3_pins),
.groups = uniphier_pxs3_groups,

20
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View file

@ -1,17 +1,7 @@
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <[email protected]>
#include <linux/kernel.h>
#include <linux/init.h>
@ -652,7 +642,7 @@ static int uniphier_sld8_get_gpio_muxval(unsigned int pin,
}
}
static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = {
static const struct uniphier_pinctrl_socdata uniphier_sld8_pindata = {
.pins = uniphier_sld8_pins,
.npins = ARRAY_SIZE(uniphier_sld8_pins),
.groups = uniphier_sld8_groups,

13
drivers/pinctrl/uniphier/pinctrl-uniphier.h
View file

@ -1,16 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PINCTRL_UNIPHIER_H__
@ -190,7 +181,7 @@ struct uniphier_pinctrl_socdata {
}
int uniphier_pinctrl_probe(struct platform_device *pdev,
struct uniphier_pinctrl_socdata *socdata);
const struct uniphier_pinctrl_socdata *socdata);
extern const struct dev_pm_ops uniphier_pinctrl_pm_ops;