From d06d88cb089ee67e41b9363f05cc432e5ccc4624 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 1 Oct 2020 21:42:28 +0530 Subject: [PATCH] clk: qcom: gpucc: Update the PLL 2x frequency The GPUCC PLL needs to lock at 2x the RCG frequency, thus update the RCG divider to '2' to lock the PLL at 2x. Change-Id: Iadeb8b03cf10c170efa8b11bf9aadc35f67ce736 Signed-off-by: Taniya Das --- drivers/clk/qcom/gpucc-holi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/gpucc-holi.c b/drivers/clk/qcom/gpucc-holi.c index 7621bbaca089..ef05bc2944cc 100644 --- a/drivers/clk/qcom/gpucc-holi.c +++ b/drivers/clk/qcom/gpucc-holi.c @@ -200,13 +200,13 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { }; static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { - F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), - F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), { } };