diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt
index f5ad2bb1e981..1fadc1b562cc 100644
--- a/bindings/arm/coresight.txt
+++ b/bindings/arm/coresight.txt
@@ -137,9 +137,10 @@ its hardware characteristcs.
 	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
 	  use the SG mode on this system.
 
-* Optional property for CATU :
+* Optional property for CATU and APSS :
 	* interrupts : Exactly one SPI may be listed for reporting the address
-	  error
+	  error for CATU and four interrupts for TGU to get trigger from four
+	  type of events.
 
 * Required property for TPDAs:
 
@@ -480,6 +481,10 @@ Example:
 		tgu-conditions = <4>;
 		tgu-regs = <4>;
 		tgu-timer-counters = <8>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_TRIGGER_HIGH>,
+			     <GIC_SPI 24 IRQ_TYPE_TRIGGER_HIGH>,
+			     <GIC_SPI 25 IRQ_TYPE_TRIGGER_HIGH>,
+			     <GIC_SPI 26 IRQ_TYPE_TRIGGER_HIGH>;
 
 		coresight-name = "coresight-tgu-ipcb";
 
diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi
index 43ed1b1c963e..f6db99b519d2 100644
--- a/qcom/holi-coresight.dtsi
+++ b/qcom/holi-coresight.dtsi
@@ -45,9 +45,9 @@
 		reg-names = "tgu-base";
 		tgu-steps = <3>;
 		tgu-conditions = <4>;
-		tgu-regs = <4>;
+		tgu-regs = <8>;
 		tgu-timer-counters = <8>;
-
+		interrupts = <0 23 1>, <0 24 1>, <0 25 1>, <0 26 1>;
 		coresight-name = "coresight-tgu-apss";
 
 		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;