From 7cf6499ef389a5c6500d10f36619b7bcdf5bd20d Mon Sep 17 00:00:00 2001
From: Yuanfang Zhang <yuanfang@qti.qualcomm.com>
Date: Mon, 21 Dec 2020 17:06:13 +0800
Subject: [PATCH] ARM: dts: msm: add DCC register list for sdxlemur

Add DCC register list to support DCC register dump
for sdxlemur.

Change-Id: I5d58d87084d173f298488d378223b74d7fa92ef9
---
 qcom/sdxlemur.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index 5378d2465d40..da49b411b2ab 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -199,6 +199,15 @@
 
 		reg-names = "dcc-base", "dcc-ram-base";
 		dcc-ram-offset = <0x12000>;
+
+		link_list1 {
+			qcom,curr-link-list = <2>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0xb204520 1 0>,
+				<DCC_READ 0xb201020 1 0>,
+				<DCC_READ 0xb201024 1 0>,
+				<DCC_READ 0xb204524 1 0>;
+		};
 	};
 
 	wdog: qcom,wdt@17817000 {