From 68cc5a6bd2dcc338d0e6aec9eadeced31435571d Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Thu, 30 Jan 2020 09:51:44 -0800 Subject: [PATCH] pinctrl: qcom: Correctly configure the SDC2 pins When the commit <9c6fe1f3cbc5d6> (pinctrl: qcom: Expose ufs_reset as gpio on Lahaina) tried to reconfigure the pins, it missed to setup the PINCTRL_PIN() entries for the same. Hence, reorder the pin numbers for proper functionality of the pins. Change-Id: Ia48156a7b0b86fc9ccaa1ddabbac7d5e1a04f37b Signed-off-by: Raghavendra Rao Ananta --- drivers/pinctrl/qcom/pinctrl-lahaina.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lahaina.c b/drivers/pinctrl/qcom/pinctrl-lahaina.c index 2657a9b7ef16..ca7b3e63c145 100644 --- a/drivers/pinctrl/qcom/pinctrl-lahaina.c +++ b/drivers/pinctrl/qcom/pinctrl-lahaina.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -328,10 +328,10 @@ static const struct pinctrl_pin_desc lahaina_pins[] = { PINCTRL_PIN(200, "GPIO_200"), PINCTRL_PIN(201, "GPIO_201"), PINCTRL_PIN(202, "GPIO_202"), - PINCTRL_PIN(203, "SDC2_CLK"), - PINCTRL_PIN(204, "SDC2_CMD"), - PINCTRL_PIN(205, "SDC2_DATA"), - PINCTRL_PIN(206, "UFS_RESET"), + PINCTRL_PIN(203, "UFS_RESET"), + PINCTRL_PIN(204, "SDC2_CLK"), + PINCTRL_PIN(205, "SDC2_CMD"), + PINCTRL_PIN(206, "SDC2_DATA"), }; #define DECLARE_MSM_GPIO_PINS(pin) \