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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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devon:add rt9471 charger
add rt9471 charger add rt9471 driver code Change-Id: I5455c4399e6ece136b622d7709670dc53a3df244 Signed-off-by: longc102 <longc102@motorola.com> Reviewed-on: https://gerrit.mot.com/2236857 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Qiong Xie <xieq2@motorola.com> Reviewed-by: Wang Wang <wangwang1@lenovo.com> Submit-Approved: Jira Key
This commit is contained in:
longc102
parent
dec0712199
commit
cb1ec726fe
5 changed files with 3576 additions and 0 deletions
21
drivers/power/rt9471_chg_mmi/Android.mk
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21
drivers/power/rt9471_chg_mmi/Android.mk
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@ -0,0 +1,21 @@
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DLKM_DIR := motorola/kernel/modules
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LOCAL_PATH := $(call my-dir)
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include $(CLEAR_VARS)
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE := rt9471_charger.ko
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ifeq ($(MMI_QC3P_TURBO_CHARGER),true)
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KERNEL_CFLAGS += CONFIG_MMI_QC3P_TURBO_CHARGER=y
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endif
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ifeq ($(MMI_QC3P_WT6670_DETECTED),true)
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KERNEL_CFLAGS += CONFIG_MMI_QC3P_WT6670_DETECTED=y
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endif
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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LOCAL_ADDITIONAL_DEPENDENCIES := $(KERNEL_MODULES_OUT)/mmi_discrete_charger_class.ko
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KBUILD_OPTIONS_GKI += GKI_OBJ_MODULE_DIR=gki
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include $(DLKM_DIR)/AndroidKernelModule.mk
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16
drivers/power/rt9471_chg_mmi/Kbuild
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drivers/power/rt9471_chg_mmi/Kbuild
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# add -Wall to try to catch everything we can.
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EXTRA_CFLAGS += -Wall
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EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/include \
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-I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/drivers/power/rt9471_chg_mmi
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ifneq ($(filter m y,$(CONFIG_MMI_QC3P_TURBO_CHARGER)),)
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EXTRA_CFLAGS += -DCONFIG_MMI_QC3P_TURBO_CHARGER
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endif
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ifneq ($(filter m y,$(CONFIG_MMI_QC3P_WT6670_DETECTED)),)
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EXTRA_CFLAGS += -DCONFIG_MMI_QC3P_WT6670_DETECTED
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endif
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obj-m += rt9471_charger.o
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KBUILD_EXTRA_SYMBOLS += $(CURDIR)/$(KBUILD_EXTMOD)/../mmi_discrete_charger/$(GKI_OBJ_MODULE_DIR)/Module.symvers
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11
drivers/power/rt9471_chg_mmi/Makefile
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drivers/power/rt9471_chg_mmi/Makefile
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KERNEL_SRC ?= /lib/modules/$(shell uname -r)/build
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all:
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$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
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modules_install:
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$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(PWD) clean
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3275
drivers/power/rt9471_chg_mmi/rt9471_charger.c
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3275
drivers/power/rt9471_chg_mmi/rt9471_charger.c
Normal file
File diff suppressed because it is too large
Load diff
253
drivers/power/rt9471_chg_mmi/rt9471_charger.h
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253
drivers/power/rt9471_chg_mmi/rt9471_charger.h
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __RT9471_CHARGER_H
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#define __RT9471_CHARGER_H
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#define RT9471_DEVICE_ADDR 0x53
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#define RT9470_DEVID 0x09
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#define RT9470D_DEVID 0x0A
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#define RT9471_DEVID 0x0D
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#define RT9471D_DEVID 0x0E
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enum rt9471_reg_addr {
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RT9471_REG_OTGCFG = 0x00,
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RT9471_REG_TOP,
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RT9471_REG_FUNCTION,
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RT9471_REG_IBUS,
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RT9471_REG_VBUS,
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RT9471_REG_PRECHG,
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RT9471_REG_REGU,
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RT9471_REG_VCHG,
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RT9471_REG_ICHG,
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RT9471_REG_CHGTIMER,
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RT9471_REG_EOC,
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RT9471_REG_INFO,
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RT9471_REG_JEITA,
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RT9471_REG_PUMPEXP,
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RT9471_REG_DPDMDET,
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RT9471_REG_STATUS,
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RT9471_REG_STAT0,
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RT9471_REG_STAT1,
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RT9471_REG_STAT2,
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RT9471_REG_STAT3,
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RT9471_REG_IRQ0 = 0x20,
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RT9471_REG_IRQ1,
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RT9471_REG_IRQ2,
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RT9471_REG_IRQ3,
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RT9471_REG_MASK0 = 0x30,
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RT9471_REG_MASK1,
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RT9471_REG_MASK2,
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RT9471_REG_MASK3,
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RT9471_REG_HIDDEN_0 = 0x40,
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RT9471_REG_HIDDEN_2 = 0x42,
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RT9471_REG_TOP_HDEN,
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RT9471_REG_BUCK_HDEN1 = 0x45,
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RT9471_REG_BUCK_HDEN2 = 0x46,
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RT9471_REG_BUCK_HDEN3 = 0x54,
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RT9471_REG_BUCK_HDEN4,
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RT9471_REG_OTG_HDEN2 = 0x58,
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RT9471_REG_BUCK_HDEN5,
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RT9471_REG_PASSCODE1 = 0xA0,
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};
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/* ========== OTGCFG 0x00 ============ */
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#define RT9471_OTGCC_MASK BIT(0)
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/* ========== TOP 0x01 ============ */
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#define RT9471_QONRST_MASK BIT(7)
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#define RT9471_DISI2CTO_MASK BIT(3)
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#define RT9471_WDTCNTRST_MASK BIT(2)
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#define RT9471_WDT_SHIFT 0
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#define RT9471_WDT_MASK 0x03
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/* ========== FUNCTION 0x02 ============ */
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#define RT9471_BATFETDIS_SHIFT 7
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#define RT9471_BATFETDIS_MASK BIT(7)
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#define RT9471_HZ_SHIFT 5
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#define RT9471_HZ_MASK BIT(5)
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#define RT9471_OTG_EN_SHIFT 1
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#define RT9471_OTG_EN_MASK BIT(1)
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#define RT9471_CHG_EN_SHIFT 0
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#define RT9471_CHG_EN_MASK BIT(0)
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/* ========== IBUS 0x03 ============ */
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#define RT9471_AICC_EN_SHIFT 7
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#define RT9471_AICC_EN_MASK BIT(7)
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#define RT9471_AUTOAICR_MASK BIT(6)
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#define RT9471_AICR_SHIFT 0
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#define RT9471_AICR_MASK 0x3F
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#define RT9471_AICR_MIN 50000
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#define RT9471_AICR_MAX 3200000
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#define RT9471_AICR_STEP 50000
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/* ========== VBUS 0x04 ============ */
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#define RT9471_VAC_OVP_SHIFT 6
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#define RT9471_VAC_OVP_MASK 0xC0
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#define RT9471_MIVR_SHIFT 0
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#define RT9471_MIVR_MASK 0x0F
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#define RT9471_MIVR_MIN 3900000
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#define RT9471_MIVR_MAX 5400000
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#define RT9471_MIVR_STEP 100000
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#define RT9471_MIVRTRACK_SHIFT 4
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#define RT9471_MIVRTRACK_MASK 0x30
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/* ========== VCHG 0x07 ============ */
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#define RT9471_VRECHG_MASK BIT(7)
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#define RT9471_CV_SHIFT 0
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#define RT9471_CV_MASK 0x7F
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#define RT9471_CV_MIN 3900000
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#define RT9471_CV_MAX 4700000
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#define RT9471_CV_STEP 10000
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/* ========== ICHG 0x08 ============ */
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#define RT9471_ICHG_SHIFT 0
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#define RT9471_ICHG_MASK 0x3F
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#define RT9471_ICHG_MIN 0
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#define RT9471_ICHG_MAX 3150000
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#define RT9471_ICHG_STEP 50000
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/* ========== CHGTIMER 0x09 ============ */
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#define RT9471_SAFETMR_EN_SHIFT 7
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#define RT9471_SAFETMR_EN_MASK BIT(7)
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#define RT9471_SAFETMR_SHIFT 4
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#define RT9471_SAFETMR_MASK 0x30
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#define RT9471_SAFETMR_MIN 5
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#define RT9471_SAFETMR_MAX 20
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#define RT9471_SAFETMR_STEP 5
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/* ========== EOC 0x0A ============ */
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#define RT9471_IEOC_SHIFT 4
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#define RT9471_IEOC_MASK 0xF0
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#define RT9471_IEOC_MIN 50000
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#define RT9471_IEOC_MAX 800000
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#define RT9471_IEOC_STEP 50000
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#define RT9471_TE_MASK BIT(1)
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#define RT9471_EOC_RST_SHIFT 0
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#define RT9471_EOC_RST_MASK BIT(0)
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/* ========== INFO 0x0B ============ */
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#define RT9471_REGRST_MASK BIT(7)
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#define RT9471_DEVID_SHIFT 3
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#define RT9471_DEVID_MASK 0x78
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#define RT9471_DEVREV_SHIFT 0
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#define RT9471_DEVREV_MASK 0x03
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/* ========== JEITA 0x0C ============ */
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#define RT9471_JEITA_EN_MASK BIT(7)
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/* ========== PUMPEXP 0x0D ============ */
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#define RT9471_PE_EN_MASK BIT(7)
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#define RT9471_PE_SEL_MASK BIT(6)
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#define RT9471_PE10_INC_MASK BIT(5)
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#define RT9471_PE20_CODE_SHIFT 0
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#define RT9471_PE20_CODE_MASK 0x1F
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#define RT9471_PE20_CODE_MIN 5500000
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#define RT9471_PE20_CODE_MAX 20000000
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#define RT9471_PE20_CODE_STEP 500000
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/* ========== DPDMDET 0x0E ============ */
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#define RT9471_BC12_EN_MASK BIT(7)
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/* ========== STATUS 0x0F ============ */
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#define RT9471_PORTSTAT_SHIFT 4
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#define RT9471_PORTSTAT_MASK 0xF0
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#define RT9471_ICSTAT_SHIFT 0
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#define RT9471_ICSTAT_MASK 0x0F
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/* ========== STAT0 0x10 ============ */
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#define RT9471_ST_VBUSGD_SHIFT 7
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#define RT9471_ST_VBUSGD_MASK BIT(7)
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#define RT9471_ST_CHGRDY_SHIFT 6
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#define RT9471_ST_CHGRDY_MASK BIT(6)
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#define RT9471_ST_IEOC_SHIFT 5
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#define RT9471_ST_IEOC_MASK BIT(5)
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#define RT9471_ST_BGCHG_SHIFT 4
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#define RT9471_ST_BGCHG_MASK BIT(4)
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#define RT9471_ST_CHGDONE_SHIFT 3
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#define RT9471_ST_CHGDONE_MASK BIT(3)
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#define RT9471_ST_BC12_DONE_SHIFT 0
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#define RT9471_ST_BC12_DONE_MASK BIT(0)
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/* ========== STAT1 0x11 ============ */
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#define RT9471_ST_MIVR_SHIFT 7
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#define RT9471_ST_MIVR_MASK BIT(7)
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#define RT9471_ST_AICR_MASK BIT(6)
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#define RT9471_ST_BATOV_MASK BIT(1)
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/* ========== STAT2 0x12 ============ */
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#define RT9471_ST_SYSMIN_SHIFT 1
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/* ========== STAT3 0x13 ============ */
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#define RT9471_ST_VACOV_SHIFT 6
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#define RT9471_ST_VACOV_MASK BIT(6)
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/* ========== HIDDEN_0 0x40 ============ */
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#define RT9471_CHIP_REV_SHIFT 5
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#define RT9471_CHIP_REV_MASK 0xE0
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/* ========== HIDDEN_2 0x42 ============ */
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#define RT9471_FORCE_HZ_SHIFT 2
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#define RT9471_FORCE_HZ_MASK BIT(2)
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/* ========== TOP_HDEN 0x43 ============ */
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#define RT9471_FORCE_EN_VBUS_SINK_SHIFT 4
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#define RT9471_FORCE_EN_VBUS_SINK_MASK BIT(4)
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/* ========== OTG_HDEN2 0x58 ============ */
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#define RT9471_REG_OTG_RES_COMP_SHIFT 4
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#define RT9471_REG_OTG_RES_COMP_MASK 0x30
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#ifdef CONFIG_MMI_QC3P_WT6670_DETECTED
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enum WT_charger_type{
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WT_CHG_TYPE_BEGIN = 0,
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WT_CHG_TYPE_FC,
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WT_CHG_TYPE_SDP,
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WT_CHG_TYPE_CDP,
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WT_CHG_TYPE_DCP,
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WT_CHG_TYPE_QC2,
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WT_CHG_TYPE_QC3,
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WT_CHG_TYPE_OCP,
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WT_CHG_TYPE_QC3P_18W,//0x8
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WT_CHG_TYPE_QC3P_27W,
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WT6670_CHG_TYPE_UNKNOWN,
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Z350_CHG_TYPE_HVDCP = 0x10,
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};
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enum mmi_qc3p_ext_iio_channels {
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/*qc3p*/
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SMB5_USB_REAL_TYPE,
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SMB5_QC3P_POWER,
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SMB5_QC3P_START_DETECT,
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SMB5_QC3P_DETECTION_READY,
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SMB5_QC3P_START_POLICY,
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SMB5_BC12_START_DETECT,
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SMB5_BC12_DETECTION_READY,
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SMB5_READ_USBIN_VOLTAGE,
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};
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static const char * const mmi_qc3p_ext_iio_chan_name[] = {
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/*qc3p*/
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[SMB5_USB_REAL_TYPE] = "wt6670_usb_real_type",
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[SMB5_QC3P_POWER] = "wt6670_usb_qc3p_power",
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[SMB5_QC3P_START_DETECT] = "wt6670_start_detection",
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[SMB5_QC3P_DETECTION_READY] "wt6670_detection_ready",
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[SMB5_QC3P_START_POLICY] "qc3p_start_policy",
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[SMB5_BC12_START_DETECT] = "wt6670_start_bc12_detection",
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[SMB5_BC12_DETECTION_READY] = "wt6670_detection_bc12_ready",
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[SMB5_READ_USBIN_VOLTAGE] = "read_usbin_voltage",
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};
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#endif
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#endif /* __RT9471_CHARGER_H */
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