From d9b978c086af0456dc0986549030e26616d04d67 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Mon, 30 Nov 2020 13:29:52 +0530 Subject: [PATCH] msm: kgsl: Don't access addr_mode_cntl registers for holi through host Sometimes probably crashdump timeout scenarios accessing addr_mode_cntl registers through the host path resulting to slave timeout issue. Hence revert this commit 'fca32c53c237("msm: kgsl: Add addr_mode_cntl registers for legacy snapshot for holi gpu")'. Change-Id: I771d9aecad69dd03d7e2ab771aee164c1cdfeabd Signed-off-by: Hareesh Gundu --- drivers/gpu/msm/adreno_a6xx_snapshot.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c index 753a90fa48e7..3bba78d461d2 100644 --- a/drivers/gpu/msm/adreno_a6xx_snapshot.c +++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c @@ -304,10 +304,6 @@ static const unsigned int a660_registers[] = { 0x0B00, 0x0B40, 0x0B80, 0x0B83, }; -static const unsigned int a619_holi_registers[] = { - /* HLSQ, SP, TPL1 */ - 0xAE00, 0xAE01, 0xBE04, 0xBE05, 0xB600, 0xB601, -}; /* * Set of registers to dump for A6XX before actually triggering crash dumper. * Registers in pairs - first value is the start offset, second @@ -1837,12 +1833,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, snapshot, a6xx_snapshot_registers, &a6xx_reg_list[i]); } - if (adreno_is_a619_holi(adreno_dev) && !crash_dump_valid) { - adreno_snapshot_registers(device, snapshot, - a619_holi_registers, - ARRAY_SIZE(a619_holi_registers) / 2); - } - /* CP_SQE indexed registers */ kgsl_snapshot_indexed_registers(device, snapshot, A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33);