From 66b3a7ff5fab1590be1ef7c50620eecd0f58c740 Mon Sep 17 00:00:00 2001 From: Chandra Sai Chidipudi Date: Tue, 24 Mar 2020 11:49:25 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add LPASS pil node for Shima Add LPASS pil node to support LPASS subsystem for Shima. Change-Id: I6bf80d455d05088742d88c4eb7daf07978ba9249 --- qcom/shima.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 702249190c3e..18839c07b97e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -11,6 +11,8 @@ #include #include #include +#include + / { model = "Qualcomm Technologies, Inc. Shima"; compatible = "qcom,shima"; @@ -1126,6 +1128,49 @@ qcom,pipe-attr-ee; }; + qcom,lpass@3700000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x3700000 0x00100>; + + vdd_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "shima-pinctrl.dtsi" From e49e29f0caf6cce36cc66099fb4ec884e5b8c2e8 Mon Sep 17 00:00:00 2001 From: Chandra Sai Chidipudi Date: Tue, 24 Mar 2020 12:27:43 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add CDSP pil node for Shima Add CDSP pil node to support CDSP subsystem for Shima. Change-Id: Ibacdc843019bade72c01799fb246b30c681ebddc --- qcom/shima.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 18839c07b97e..52caa7d35ced 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1171,6 +1171,50 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + + qcom,turing@a300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xa300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MXC_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "shima-pinctrl.dtsi" From 1a9e556b5fb39348e61f929f9e451db295c348bf Mon Sep 17 00:00:00 2001 From: Chandra Sai Chidipudi Date: Tue, 24 Mar 2020 12:49:17 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add Modem pil node for Shima Add Modem pil node to support Modem subsystem for Shima. Change-Id: I8e93db667b2e8dbc66c473203b8a3f4e4ab7c9d6 --- qcom/shima.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 52caa7d35ced..bca0102f8ce0 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1128,6 +1128,52 @@ qcom,pipe-attr-ee; }; + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MODEM_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <4>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,firmware-name = "modem"; + memory-region = <&pil_mpss_wlan_mem>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + qcom,lpass@3700000 { compatible = "qcom,pil-tz-generic"; reg = <0x3700000 0x00100>;