From 5cabfa5faf1e40b32180b35df3c8e584317e3d87 Mon Sep 17 00:00:00 2001 From: Hiren Gohel Date: Sun, 1 Nov 2020 23:29:13 +0530 Subject: [PATCH] ARM: dts: msm: Add eMMC card support for monaco Add eMMC card support for monaco. Change-Id: I77b7ea4f7b10a4eccc7e0b7bcd65343cb3362995 --- qcom/monaco-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++++++ qcom/monaco-rumi.dtsi | 16 ++++++++++ qcom/monaco.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index f98e24512fec..44e0c9de0410 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -746,4 +746,55 @@ }; }; }; + /* SDC pin type */ + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + }; diff --git a/qcom/monaco-rumi.dtsi b/qcom/monaco-rumi.dtsi index 06eae741f70b..e0c8369a741f 100644 --- a/qcom/monaco-rumi.dtsi +++ b/qcom/monaco-rumi.dtsi @@ -24,3 +24,19 @@ }; #include "monaco-stub-regulator.dtsi" +&sdhc_1 { + status = "ok"; + + cap-mmc-highspeed; + max-frequency = <50000000>; + + vdd-supply = <&L25A>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 270000>; + + vdd-io-supply = <&L15A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 250000>; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 47415a453570..61d40ae99ba4 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -21,6 +21,7 @@ aliases { serial0 = &qupv3_se6_2uart; hsuart0 = &qupv3_se5_4uart; + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ }; firmware: firmware {}; @@ -1004,6 +1005,69 @@ interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>,<1600 1600>, + /* 25 MB/s */ + <25600 250000>,<50000 133320>, + /* 50 MB/s */ + <51200 250000>,<65000 133320>, + /* 100 MB/s */ + <102400 250000>,<65000 133320>, + /* 200 MB/s */ + <204800 800000>,<200000 300000>, + /* 400 MB/s */ + <204800 800000>,<200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>,<1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642E 0x0 0x01 0x2c010800 0x80040868>; + + no-sd; + no-sdio; + + bus-width = <8>; + non-removable; + supports-cqe; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; }; #include "monaco-pinctrl.dtsi"