diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_core.c b/drivers/power/mmi_parallel_charger/mmi_charger_core.c
index 23558540107a..329b34fa6a1a 100644
--- a/drivers/power/mmi_parallel_charger/mmi_charger_core.c
+++ b/drivers/power/mmi_parallel_charger/mmi_charger_core.c
@@ -600,6 +600,7 @@ static enum power_supply_property mmi_chrg_mgr_props[] = {
 	POWER_SUPPLY_PROP_CHARGE_COUNTER,
 	POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL,
 	POWER_SUPPLY_PROP_NUM_SYSTEM_TEMP_LEVELS,
+	POWER_SUPPLY_PROP_CP_ENABLE,
 };
 
 static int mmi_chrg_mgr_get_property(struct power_supply *psy,
@@ -657,6 +658,9 @@ static int mmi_chrg_mgr_get_property(struct power_supply *psy,
 	case POWER_SUPPLY_PROP_NUM_SYSTEM_TEMP_LEVELS:
 		val->intval = chip->thermal_levels;
 		break;
+	case POWER_SUPPLY_PROP_CP_ENABLE:
+		val->intval = !chip->cp_disable;
+		break;
 	default:
 		return -EINVAL;
 
@@ -695,7 +699,11 @@ static int mmi_chrg_mgr_set_property(struct power_supply *psy,
 			return -EINVAL;
 		chip->pd_volt_max= val->intval;
 		break;
-
+	case POWER_SUPPLY_PROP_CP_ENABLE:
+		if (chip->pd_pps_support
+			&& !chip->factory_mode)
+			mmi_chrg_enable_all_cp(chip, val->intval);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -712,6 +720,7 @@ static int mmi_chrg_mgr_is_writeable(struct power_supply *psy,
 	case POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL:
 	case POWER_SUPPLY_PROP_PD_CURRENT_MAX:
 	case POWER_SUPPLY_PROP_PD_VOLTAGE_MAX:
+	case POWER_SUPPLY_PROP_CP_ENABLE:
 		ret = 1;
 		break;
 	default:
diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_core.h b/drivers/power/mmi_parallel_charger/mmi_charger_core.h
index 9eeb0696e1c4..e4a84c287325 100644
--- a/drivers/power/mmi_parallel_charger/mmi_charger_core.h
+++ b/drivers/power/mmi_parallel_charger/mmi_charger_core.h
@@ -153,6 +153,7 @@ struct mmi_charger_manager {
 	bool			factory_mode;
 	bool			suspended;
 	bool			awake;
+	bool			cp_disable;
 
 	int *debug_mask;
 	int mmi_pd_pdo_idx;	/*request the pdo idx of PD*/
diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_policy.h b/drivers/power/mmi_parallel_charger/mmi_charger_policy.h
index b24392e75166..e3dfc285caa8 100644
--- a/drivers/power/mmi_parallel_charger/mmi_charger_policy.h
+++ b/drivers/power/mmi_parallel_charger/mmi_charger_policy.h
@@ -31,4 +31,5 @@ extern int mmi_chrg_policy_init(struct mmi_charger_manager *chip,
 								struct mmi_chrg_dts_info *chrg_dts,
 								int chrg_cnt);
 extern void mmi_chrg_policy_clear(struct mmi_charger_manager *chip);
+extern void mmi_chrg_enable_all_cp(struct mmi_charger_manager *chip, int val);
 #endif
diff --git a/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c b/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c
index ca8b3937b453..a91f0fc53790 100644
--- a/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c
+++ b/drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c
@@ -273,6 +273,45 @@ static void chrg_policy_error_recovery(struct mmi_charger_manager *chip,
 	return;
 }
 
+void mmi_chrg_enable_all_cp(struct mmi_charger_manager *chip, int val)
+{
+	struct mmi_cp_policy_dev *chrg_list = &g_chrg_list;
+	bool enable = !!val;
+
+	mmi_chrg_dbg(chip, PR_MOTO,"enable all cp = %d\n", enable);
+	if (enable) {
+		if (chip->cp_disable == false)
+			return;
+
+		cancel_delayed_work_sync(&chip->mmi_chrg_sm_work);
+		mmi_chrg_sm_move_state(chip, PM_STATE_CHRG_PUMP_ENTRY);
+		chip->cp_disable = false;
+		schedule_delayed_work(&chip->mmi_chrg_sm_work,
+				msecs_to_jiffies(0));
+
+	} else {
+		if(chrg_list->cp_master
+			&& !chrg_list->chrg_dev[CP_MASTER]->charger_enabled)
+			return;
+
+		cancel_delayed_work_sync(&chip->mmi_chrg_sm_work);
+
+		chip->cp_disable = true;
+		if (chrg_list->cp_slave
+			&& chrg_list->chrg_dev[CP_SLAVE]->charger_enabled) {
+			mmi_enable_charging(chrg_list->chrg_dev[CP_SLAVE], false);
+		}
+
+		if (chrg_list->cp_master
+			&& chrg_list->chrg_dev[CP_MASTER]->charger_enabled) {
+			mmi_enable_charging(chrg_list->chrg_dev[CP_MASTER], false);
+		}
+
+		mmi_chrg_sm_move_state(chip, PM_STATE_RECOVERY_SW);
+		schedule_delayed_work(&chip->mmi_chrg_sm_work,
+				msecs_to_jiffies(0));
+	}
+}
 
 #define HEARTBEAT_SHORT_DELAY_MS 1000
 #define HEARTBEAT_lOOP_WAIT_MS 3000
@@ -611,6 +650,7 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
 		break;
 	case PM_STATE_SW_LOOP:
 		if (chip->pd_pps_support
+			&& chip->cp_disable == false
 			&& vbatt_volt > chip->pl_chrg_vbatt_min
 			&& chrg_step->pres_chrg_step != chip->chrg_step_nums - 1
 			&& chrg_step->chrg_step_cc_curr >=