From cd72ed7a2a0d5aec470e556e436d5b303fce3f60 Mon Sep 17 00:00:00 2001 From: Adam Brickman Date: Fri, 6 Jul 2018 15:35:17 -0500 Subject: [PATCH] ASoC: cs35l41: Rev B0 register defaults * Fix register defaults that changed with chip revision B0. * regmap_register_patch() has a bug which will cause register writes to be delivered to the chip, but NOT the regcache. This can cause the regcache to become out of sync with the actual state of the registers. Changed the usage of this function to regmap_multi_reg_write() to avoid this problem. SQA-860 Mot-CRs-fixed: (CR): River: AoU bringup on Marley+Prince Change-Id: I512cffd656fdf942b7fcafc2a0473a7449cf2547 Signed-off-by: Adam Brickman Reviewed-on: https://gerrit.mot.com/1238848 SME-Granted: SME Approvals Granted Tested-by: Jira Key SLTApproved: Slta Waiver Reviewed-by: Konstantin Makariev Submit-Approved: Jira Key --- sound/soc/codecs/cs35l41.c | 6 +++++- sound/soc/codecs/cs35l41.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index 9bcc629d4dda..2bab24a09f4d 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -1870,7 +1870,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, switch (reg_revid) { case CS35L41_REVID_A0: - ret = regmap_register_patch(cs35l41->regmap, + ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_reva0_errata_patch, ARRAY_SIZE(cs35l41_reva0_errata_patch)); if (ret < 0) { @@ -1878,6 +1878,10 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, "Failed to apply A0 errata patch %d\n", ret); goto err; } + break; + case CS35L41_REVID_B0: + regmap_write(cs35l41->regmap, CS35L41_BSTCVRT_DCM_CTRL, 0x51); + break; } ret = cs35l41_otp_unpack(cs35l41); diff --git a/sound/soc/codecs/cs35l41.h b/sound/soc/codecs/cs35l41.h index 9cce2801ce2e..6866dd3ea42e 100644 --- a/sound/soc/codecs/cs35l41.h +++ b/sound/soc/codecs/cs35l41.h @@ -696,6 +696,7 @@ #define CS35L41R_CHIP_ID 0x35b40 #define CS35L41_MTLREVID_MASK 0x0F #define CS35L41_REVID_A0 0xA0 +#define CS35L41_REVID_B0 0xB0 #define CS35L41_DSP_N_RX_RATES 8 #define CS35L41_DSP_N_TX_RATES 8