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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 20:33:58 -04:00
mmc: cqhci: Add inline crypto support to cqhci
Wire up cqhci.c with the eMMC Crypto API and support for block layer inline encryption additions and the keyslot manager. Ported and fixed the merged conflicts in cqhci.c file Added new member in cqhci_host to get platform device from sdhci during cqhci_pltfm_init(). (cherry picked from mainline kernel_msm-4.19 commit 2543833e). Conflicts: drivers/mmc/host/cqhci.c Test: 1. Device booted upto UI with File Based Encryption enabled. 2. Key insertion using fscryptctl tool. 3. Created new files under /data and checked retention across multiple re-boots. 4. vts_kernel_encryption_test tests. 5. check_encryption test for verifying metadata encryption. Change-Id: I6860cd29d6f044f559385d438048b850faf9a8be Signed-off-by: Neeraj Soni <neersoni@codeaurora.org> Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
This commit is contained in:
Neeraj Soni
Gerrit - the friendly Code Review server
parent
bec27fe2bc
commit
cd86102b66
2 changed files with 101 additions and 1 deletions
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@ -18,6 +18,7 @@
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#include <linux/mmc/card.h>
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#include "cqhci.h"
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#include "cqhci-crypto.h"
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#define DCMD_SLOT 31
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#define NUM_SLOTS 32
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@ -138,6 +139,8 @@ static void cqhci_dumpregs(struct cqhci_host *cq_host)
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cqhci_readl(cq_host, CQHCI_CRI),
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cqhci_readl(cq_host, CQHCI_CRA));
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cqhci_crypto_debug(cq_host);
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if (cq_host->ops->dumpregs)
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cq_host->ops->dumpregs(mmc);
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else
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@ -258,6 +261,11 @@ static void __cqhci_enable(struct cqhci_host *cq_host)
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if (cq_host->caps & CQHCI_TASK_DESC_SZ_128)
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cqcfg |= CQHCI_TASK_DESC_SZ;
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if (cqhci_host_is_crypto_supported(cq_host)) {
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cqhci_crypto_enable(cq_host);
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cqcfg |= CQHCI_ICE_ENABLE;
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}
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cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
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cqhci_writel(cq_host, lower_32_bits(cq_host->desc_dma_base),
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@ -290,6 +298,9 @@ static void __cqhci_disable(struct cqhci_host *cq_host)
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{
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u32 cqcfg;
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if (cqhci_host_is_crypto_supported(cq_host))
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cqhci_crypto_disable(cq_host);
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cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
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cqcfg &= ~CQHCI_ENABLE;
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cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
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@ -303,6 +314,8 @@ int cqhci_deactivate(struct mmc_host *mmc)
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{
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struct cqhci_host *cq_host = mmc->cqe_private;
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cqhci_crypto_suspend(cq_host);
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if (cq_host->enabled && cq_host->activated)
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__cqhci_disable(cq_host);
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@ -561,6 +574,30 @@ static inline int cqhci_tag(struct mmc_request *mrq)
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return mrq->cmd ? DCMD_SLOT : mrq->tag;
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}
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static inline
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void cqhci_prep_crypto_desc(struct cqhci_host *cq_host, u64 *task_desc,
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u64 ice_ctx)
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{
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__le64 *ice_desc = NULL;
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if (cq_host->caps & CQHCI_CAP_CRYPTO_SUPPORT) {
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/*
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* Get the address of ice context for the given task descriptor.
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* ice context is present in the upper 64bits of task descriptor
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* ice_conext_base_address = task_desc + 8-bytes
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*/
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ice_desc = (__le64 *)((u8 *)task_desc +
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CQHCI_TASK_DESC_ICE_PARAM_OFFSET);
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memset(ice_desc, 0, CQHCI_TASK_DESC_ICE_PARAMS_SIZE);
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/*
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* Assign upper 64bits data of task descritor with ice context
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*/
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if (ice_ctx)
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*ice_desc = cpu_to_le64(ice_ctx);
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}
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}
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static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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int err = 0;
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@ -569,6 +606,7 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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int tag = cqhci_tag(mrq);
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struct cqhci_host *cq_host = mmc->cqe_private;
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unsigned long flags;
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u64 ice_ctx = 0;
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if (!cq_host->enabled) {
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pr_err("%s: cqhci: not enabled\n", mmc_hostname(mmc));
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@ -592,9 +630,17 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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}
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if (mrq->data) {
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err = cqhci_crypto_get_ctx(cq_host, mrq, &ice_ctx);
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if (err) {
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pr_err("%s: failed to retrieve crypto ctx for tag %d\n",
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mmc_hostname(mmc), tag);
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goto out;
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}
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task_desc = (__le64 __force *)get_desc(cq_host, tag);
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cqhci_prep_task_desc(mrq, &data, 1);
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*task_desc = cpu_to_le64(data);
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cqhci_prep_crypto_desc(cq_host, task_desc, ice_ctx);
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err = cqhci_prep_tran_desc(mrq, cq_host, tag);
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if (err) {
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pr_err("%s: cqhci: failed to setup tx desc: %d\n",
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@ -628,6 +674,9 @@ out_unlock:
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if (err)
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cqhci_post_req(mmc, mrq);
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if (mrq->data)
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cqhci_complete_crypto_desc(cq_host, mrq, NULL);
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out:
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return err;
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}
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@ -635,7 +684,15 @@ out_unlock:
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static void cqhci_crypto_update_queue(struct mmc_host *mmc,
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struct request_queue *queue)
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{
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//struct cqhci_host *cq_host = mmc->cqe_private;
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struct cqhci_host *cq_host = mmc->cqe_private;
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if (cq_host->caps & CQHCI_CAP_CRYPTO_SUPPORT) {
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if (queue)
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cqhci_crypto_setup_rq_keyslot_manager(cq_host, queue);
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else
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pr_err("%s can not register keyslot manager\n",
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mmc_hostname(mmc));
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}
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}
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#endif
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@ -755,6 +812,8 @@ static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag)
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data = mrq->data;
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if (data) {
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cqhci_complete_crypto_desc(cq_host, mrq, NULL);
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if (data->error)
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data->bytes_xfered = 0;
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else
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@ -942,6 +1001,8 @@ static void cqhci_recovery_start(struct mmc_host *mmc)
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pr_debug("%s: cqhci: %s\n", mmc_hostname(mmc), __func__);
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cqhci_crypto_reset(cq_host);
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WARN_ON(!cq_host->recovery_halt);
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cqhci_halt(mmc, CQHCI_START_HALT_TIMEOUT);
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@ -1062,6 +1123,8 @@ static void cqhci_recovery_finish(struct mmc_host *mmc)
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cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
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cqhci_crypto_recovery_finish(cq_host);
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pr_debug("%s: cqhci: recovery done\n", mmc_hostname(mmc));
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}
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@ -1103,6 +1166,11 @@ struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev)
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dev_err(&pdev->dev, "failed to remap cqhci regs\n");
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return ERR_PTR(-EBUSY);
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}
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#ifdef CONFIG_MMC_CQHCI_CRYPTO_QTI
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cq_host->pdev = pdev;
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#endif /* CONFIG_MMC_CQHCI_CRYPTO_QTI */
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dev_dbg(&pdev->dev, "CMDQ ioremap: done\n");
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return cq_host;
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@ -1148,6 +1216,13 @@ int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc,
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spin_lock_init(&cq_host->lock);
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err = cqhci_host_init_crypto(cq_host);
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if (err) {
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pr_err("%s: CQHCI version %u.%02u Crypto init failed err %d\n",
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mmc_hostname(mmc), cqhci_ver_major(cq_host),
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cqhci_ver_minor(cq_host), err);
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}
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init_completion(&cq_host->halt_comp);
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init_waitqueue_head(&cq_host->wait_queue);
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@ -32,6 +32,7 @@
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#define CQHCI_DCMD 0x00001000
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#define CQHCI_TASK_DESC_SZ 0x00000100
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#define CQHCI_ENABLE 0x00000001
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#define CQHCI_ICE_ENABLE 0x00000002
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/* control */
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#define CQHCI_CTL 0x0C
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@ -148,11 +149,20 @@
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#define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
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#define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
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#define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
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#define DATA_UNIT_NUM(x) (((u64)(x) & 0xFFFFFFFF) << 0)
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#define CRYPTO_CONFIG_INDEX(x) (((u64)(x) & 0xFF) << 32)
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#define CRYPTO_ENABLE(x) (((u64)(x) & 0x1) << 47)
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/* ICE context is present in the upper 64bits of task descriptor */
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#define CQHCI_TASK_DESC_ICE_PARAM_OFFSET 8
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/* ICE descriptor size */
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#define CQHCI_TASK_DESC_ICE_PARAMS_SIZE 8
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struct cqhci_host_ops;
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struct mmc_host;
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struct mmc_request;
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struct cqhci_slot;
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struct cqhci_host;
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/* CCAP - Crypto Capability 100h */
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union cqhci_crypto_capabilities {
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@ -240,6 +250,7 @@ struct cqhci_host_crypto_variant_ops {
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struct cqhci_host {
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const struct cqhci_host_ops *ops;
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void __iomem *mmio;
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void __iomem *icemmio;
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struct mmc_host *mmc;
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spinlock_t lock;
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@ -255,6 +266,7 @@ struct cqhci_host {
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u32 dcmd_slot;
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u32 caps;
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#define CQHCI_TASK_DESC_SZ_128 0x1
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#define CQHCI_CAP_CRYPTO_SUPPORT 0x2
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u32 quirks;
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#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
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@ -291,6 +303,19 @@ struct cqhci_host {
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struct completion halt_comp;
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wait_queue_head_t wait_queue;
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struct cqhci_slot *slot;
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const struct cqhci_host_crypto_variant_ops *crypto_vops;
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#ifdef CONFIG_MMC_CQHCI_CRYPTO
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union cqhci_crypto_capabilities crypto_capabilities;
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union cqhci_crypto_cap_entry *crypto_cap_array;
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u32 crypto_cfg_register;
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#ifdef CONFIG_BLK_INLINE_ENCRYPTION
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struct keyslot_manager *ksm;
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#endif /* CONFIG_BLK_INLINE_ENCRYPTION */
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#endif /* CONFIG_MMC_CQHCI_CRYPTO */
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#ifdef CONFIG_MMC_CQHCI_CRYPTO_QTI
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struct platform_device *pdev;
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#endif /* CONFIG_MMC_CQHCI_CRYPTO_QTI */
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};
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struct cqhci_host_ops {
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