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dt-bindings: clk: meson: add sm1 periph clock controller bindings
Update the documentation to support clock driver for the Amlogic SM1 SoC and expose the GP1, DSU and the CPU 1, 2 & 3 clocks. SM1 clock tree is very close, the main differences are : - each CPU core can achieve a different frequency, albeit a common PLL - a similar tree as the clock tree has been added for the DynamIQ Shared Unit - has a new GP1 PLL used for the DynamIQ Shared Unit - SM1 has additional clocks like for CSI, NanoQ an other components Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
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@ -138,5 +138,10 @@
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#define CLKID_VDEC_HEVCF 210
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#define CLKID_TS 212
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#define CLKID_CPUB_CLK 224
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#define CLKID_GP1_PLL 243
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#define CLKID_DSU_CLK 252
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#endif /* __G12A_CLKC_H */
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