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Merge "msm: kgsl: Add hwcg table for A680"

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qctecmdr 2021-03-26 01:27:21 -07:00 • committed by Gerrit - the friendly Code Review server
commit cdb04ea990
2 changed files with 66 additions and 3 deletions
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9
drivers/gpu/msm/a6xx_reg.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _A6XX_REG_H
@ -544,6 +544,13 @@
#define A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0011c
#define A6XX_RBBM_CLOCK_HYST_HLSQ 0x0011d
#define A6XX_GMUAO_GMU_CGC_MODE_CNTL 0x23b09
#define A6XX_GMUAO_GMU_CGC_DELAY_CNTL 0x23b0a
#define A6XX_GMUAO_GMU_CGC_HYST_CNTL 0x23b0b
#define A6XX_GMUCX_GMU_WFI_CONFIG 0x1f802
#define A6XX_GMUGX_GMU_SP_RF_CONTROL_0 0x1a883
#define A6XX_GMUGX_GMU_SP_RF_CONTROL_1 0x1a884
/* DBGC_CFG registers */
#define A6XX_DBGC_CFG_DBGBUS_SEL_A 0x600
#define A6XX_DBGC_CFG_DBGBUS_SEL_B 0x601

60
drivers/gpu/msm/adreno-gpulist.h
View file

@ -1167,6 +1167,62 @@ static const struct adreno_reglist a640_hwcg_regs[] = {
{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};
static const struct adreno_reglist a680_hwcg_regs[] = {
{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
{A6XX_RBBM_CLOCK_HYST_TP0, 0x00000000},
{A6XX_RBBM_CLOCK_HYST2_TP0, 0x00000000},
{A6XX_RBBM_CLOCK_HYST3_TP0, 0x00000000},
{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00000000},
{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
{A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
{A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
{A6XX_RBBM_ISDB_CNT, 0x00000182},
{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
{A6XX_GMUAO_GMU_CGC_MODE_CNTL, 0x00020202},
{A6XX_GMUAO_GMU_CGC_DELAY_CNTL, 0x00010111},
{A6XX_GMUAO_GMU_CGC_HYST_CNTL, 0x00005555},
{A6XX_GMUCX_GMU_WFI_CONFIG, 0x00000002},
{A6XX_GMUGX_GMU_SP_RF_CONTROL_0, 0x00000001},
{A6XX_GMUGX_GMU_SP_RF_CONTROL_1, 0x00000001},
};
/* These apply to a640, a680, a612 and a610 */
static const struct adreno_reglist a640_vbif_regs[] = {
{A6XX_GBIF_QSB_SIDE0, 0x00071620},
@ -1331,8 +1387,8 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
.sqefw_name = "a630_sqe.fw",
.gmufw_name = "a640_gmu.bin",
.zap_name = "a640_zap",
.hwcg = a640_hwcg_regs,
.hwcg_count = ARRAY_SIZE(a640_hwcg_regs),
.hwcg = a680_hwcg_regs,
.hwcg_count = ARRAY_SIZE(a680_hwcg_regs),
.vbif = a640_vbif_regs,
.vbif_count = ARRAY_SIZE(a640_vbif_regs),
.hang_detect_cycles = 0xcfffff,