ARM: dts: msm: enable io coherency on unsecure cb for Lahaina

Enable io coherency for non-secure context bank for lahaina
target. This support is not needed for secure context bank because
secure cb only maps secure buffers which are not cpu accessible.

Change-Id: If693842c68fa714c6eee5c62437432ffbe80f749
This commit is contained in:
Dhaval Patel 2020-06-04 10:17:16 -07:00
commit cdb6907875

View file

@ -662,6 +662,7 @@
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-earlymap; /* for cont-splash */
dma-coherent-hint-cached;
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {