A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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ARM: dts: msm: Add etm save/restore for Lahaina

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Add device tree node to support ETM register save/restore function
across power collapse.

Change-Id: I5febc6634dfc1712e884ccc609fc2a3834480bf8
This commit is contained in:
Tingwei Zhang 2019-12-17 16:28:08 +08:00
commit ceefcbf0be
1 changed files with 88 additions and 0 deletions
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88
qcom/lahaina.dtsi
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@ -1002,6 +1002,94 @@
qcom,rtb-size = <0x100000>;
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x200000>;