From cf5f6f8f0ecce4be4379370cb6ab1e802fdc6658 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 25 Sep 2020 10:47:37 +0530 Subject: [PATCH] ARM: dts: msm: Add device node for llcc node on SM6150 Add device node for last level cache controller on SM6150. Change-Id: Id8e6c6ded90e02e594f583aac179222fae359bf5 --- bindings/arm/msm/qcom,llcc.txt | 2 +- qcom/sm6150.dtsi | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 6bddb3cbb70c..bf052f36b6de 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,7 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,sdxlemur-llcc" or "qcom,yupik-llcc" or "qcom,sm8150-llcc" - or "qcom,sdmshrike-llcc" + or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 211d20ade731..6460aff6ac7e 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1001,6 +1001,13 @@ clock-frequency = <32768>; }; + cache-controller@9200000 { + compatible = "qcom,sm6150-llcc"; + reg = <0x9200000 0x50000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc";