From 026aa276ab5af94a21dd20791b41f29d85059598 Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <mmandaya@quicinc.com>
Date: Mon, 9 Mar 2020 15:57:06 -0700
Subject: [PATCH] ARM: dts: msm: Open NOM_L1 gpu powerlevel for A660 v1

Expose NOM_L1 power level for A660 v1 devices.

Change-Id: I3ca084c3c6fb24a9ffc26c33505d01c6f40b52a8
---
 qcom/lahaina-gpu.dtsi | 32 +++++++++++++++++++++++---------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi
index a0f8ee1700f7..00a629d1c01e 100644
--- a/qcom/lahaina-gpu.dtsi
+++ b/qcom/lahaina-gpu.dtsi
@@ -31,7 +31,7 @@
 
 		qcom,chipid = <0x06060000>;
 
-		qcom,initial-pwrlevel = <4>;
+		qcom,initial-pwrlevel = <5>;
 
 		qcom,no-nap;
 
@@ -121,8 +121,8 @@
 
 			qcom,gpu-pwrlevel@0 {
 				reg = <0>;
-				qcom,gpu-freq = <676000000>;
-				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+				qcom,gpu-freq = <710000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 
 				qcom,bus-freq-ddr7 = <11>;
 				qcom,bus-min-ddr7 = <11>;
@@ -135,6 +135,20 @@
 
 			qcom,gpu-pwrlevel@1 {
 				reg = <1>;
+				qcom,gpu-freq = <676000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq-ddr7 = <11>;
+				qcom,bus-min-ddr7 = <11>;
+				qcom,bus-max-ddr7 = <11>;
+
+				qcom,bus-freq-ddr8 = <10>;
+				qcom,bus-min-ddr8 = <10>;
+				qcom,bus-max-ddr8 = <11>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
 				qcom,gpu-freq = <608000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
@@ -147,8 +161,8 @@
 				qcom,bus-max-ddr8 = <11>;
 			};
 
-			qcom,gpu-pwrlevel@2 {
-				reg = <2>;
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
 				qcom,gpu-freq = <540000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
@@ -161,8 +175,8 @@
 				qcom,bus-max-ddr8 = <9>;
 			};
 
-			qcom,gpu-pwrlevel@3 {
-				reg = <3>;
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
 				qcom,gpu-freq = <443000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
@@ -175,8 +189,8 @@
 				qcom,bus-max-ddr8 = <9>;
 			};
 
-			qcom,gpu-pwrlevel@4 {
-				reg = <4>;
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
 				qcom,gpu-freq = <315000000>;
 				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;