mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: SoC driver updates for v4.15
This branch contains platform-related driver updates for ARM and ARM64,
these are the areas that bring the changes:
New drivers:
- Driver support for Renesas R-Car V3M (R8A77970)
- Power management support for Amlogic GX
- A new driver for the Tegra BPMP thermal sensor
- A new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- The usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa, uniphier
and mediatek families.
- Updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo Pieralisi.
Changes specific to some ARM-based SoC
- The Freescale/NXP DPAA QBMan drivers from PowerPC can now work
on ARM as well.
- Several changes for power management on Broadcom SoCs
- Various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek
- Minor Cleanups for Samsung, TI OMAP SoCs
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"This branch contains platform-related driver updates for ARM and
ARM64, these are the areas that bring the changes:
New drivers:
- driver support for Renesas R-Car V3M (R8A77970)
- power management support for Amlogic GX
- a new driver for the Tegra BPMP thermal sensor
- a new bus driver for Technologic Systems NBUS
Changes for subsystems that prefer to merge through arm-soc:
- the usual updates for reset controller drivers from Philipp Zabel,
with five added drivers for SoCs in the arc, meson, socfpa,
uniphier and mediatek families
- updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla,
Heiner Kallweit and Lorenzo Pieralisi
Changes specific to some ARM-based SoC
- the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on
ARM as well
- several changes for power management on Broadcom SoCs
- various improvements on Qualcomm, Broadcom, Amlogic, Atmel,
Mediatek
- minor Cleanups for Samsung, TI OMAP SoCs"
[ NOTE! This doesn't work without the previous ARM SoC device-tree pull,
because the R8A77970 driver is missing a header file that came from
that pull.
The fact that this got merged afterwards only fixes it at this point,
and bisection of that driver will fail if/when you walk into the
history of that driver. - Linus ]
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits)
soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader
bus: add driver for the Technologic Systems NBUS
memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg()
soc: qcom: remove unused label
soc: amlogic: gx pm domain: add PM and OF dependencies
drivers/firmware: psci_checker: Add missing destroy_timer_on_stack()
dt-bindings: power: add amlogic meson power domain bindings
soc: amlogic: add Meson GX VPU Domains driver
soc: qcom: Remote filesystem memory driver
dt-binding: soc: qcom: Add binding for rmtfs memory
of: reserved_mem: Accessor for acquiring reserved_mem
of/platform: Generalize /reserved-memory handling
soc: mediatek: pwrap: fix fatal compiler error
soc: mediatek: pwrap: fix compiler errors
arm64: mediatek: cleanup message for platform selection
soc: Allow test-building of MediaTek drivers
soc: mediatek: place Kconfig for all SoC drivers under menu
soc: mediatek: pwrap: add support for MT7622 SoC
soc: mediatek: pwrap: add common way for setup CS timing extenstion
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
..
This commit is contained in:
Linus Torvalds
commit
cf9b0772f2
110 changed files with 6933 additions and 996 deletions
|
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@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY.
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|||
|
||||
Required properties:
|
||||
- compatible : should contain one of these
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||||
"brcm,brcmstb-ddr-phy-v71.1"
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"brcm,brcmstb-ddr-phy-v72.0"
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"brcm,brcmstb-ddr-phy-v225.1"
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"brcm,brcmstb-ddr-phy-v240.1"
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"brcm,brcmstb-ddr-phy-v240.2"
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@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh
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Power-Down (SRPD), among other things.
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||||
Required properties:
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||||
- compatible : should contain "brcm,brcmstb-memc-ddr"
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- compatible : should contain one of these
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"brcm,brcmstb-memc-ddr-rev-b.2.2"
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"brcm,brcmstb-memc-ddr"
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- reg : the MEMC DDR register range
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Example:
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|
|
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|
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@ -4,7 +4,6 @@ Properties:
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|||
- compatible : should contain two values. First value must be one from following list:
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- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
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- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
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- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
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- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
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- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
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- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
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|
|
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|||
|
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@ -18,6 +18,8 @@ Required properties:
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|||
* Core, iface, and bus clocks required for "qcom,scm"
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- clock-names: Must contain "core" for the core clock, "iface" for the interface
|
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clock and "bus" for the bus clock per the requirements of the compatible.
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- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
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download mode control register (optional)
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Example for MSM8916:
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|
|
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@ -0,0 +1,27 @@
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DDR PHY Front End (DPFE) for Broadcom STB
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=========================================
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DPFE and the DPFE firmware provide an interface for the host CPU to
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communicate with the DCPU, which resides inside the DDR PHY.
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There are three memory regions for interacting with the DCPU. These are
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specified in a single reg property.
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Required properties:
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- compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
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or "brcm,dpfe-cpu"
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- reg: must reference three register ranges
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- start address and length of the DCPU register space
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- start address and length of the DCPU data memory space
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- start address and length of the DCPU instruction memory space
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- reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
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they must be in the same order as the register declarations
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Example:
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dpfe_cpu0: dpfe-cpu@f1132000 {
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compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
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reg = <0xf1132000 0x180
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0xf1134000 0x1000
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0xf1138000 0x4000>;
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reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
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};
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@ -11,3 +11,156 @@ Required properties:
|
|||
|
||||
The experimental -viper variants are for running Linux on the 3384's
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BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
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Power management
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----------------
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For power management (particularly, S2/S3/S5 system suspend), the following SoC
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components are needed:
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= Always-On control block (AON CTRL)
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This hardware provides control registers for the "always-on" (even in low-power
|
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modes) hardware, such as the Power Management State Machine (PMSM).
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Required properties:
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- compatible : should be one of
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"brcm,bcm7425-aon-ctrl"
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"brcm,bcm7429-aon-ctrl"
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"brcm,bcm7435-aon-ctrl" and
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"brcm,brcmstb-aon-ctrl"
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- reg : the register start and length for the AON CTRL block
|
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Example:
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syscon@410000 {
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compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
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reg = <0x410000 0x400>;
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};
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= Memory controllers
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A Broadcom STB SoC typically has a number of independent memory controllers,
|
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each of which may have several associated hardware blocks, which are versioned
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independently (control registers, DDR PHYs, etc.). One might consider
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describing these controllers as a parent "memory controllers" block, which
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contains N sub-nodes (one for each controller in the system), each of which is
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associated with a number of hardware register resources (e.g., its PHY.
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== MEMC (MEMory Controller)
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Represents a single memory controller instance.
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Required properties:
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- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
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- ranges : should contain the child address in the parent address
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space, must be 0 here, and the register start and length of
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the entire memory controller (including all sub nodes: DDR PHY,
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arbiter, etc.)
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- #address-cells : must be 1
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- #size-cells : must be 1
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Example:
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memory-controller@0 {
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compatible = "brcm,brcmstb-memc", "simple-bus";
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ranges = <0x0 0x0 0xa000>;
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#address-cells = <1>;
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#size-cells = <1>;
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memc-arb@1000 {
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...
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};
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memc-ddr@2000 {
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...
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};
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ddr-phy@6000 {
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...
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};
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};
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Should contain subnodes for any of the following relevant hardware resources:
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== DDR PHY control
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||||
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Control registers for this memory controller's DDR PHY.
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Required properties:
|
||||
- compatible : should contain one of these
|
||||
"brcm,brcmstb-ddr-phy-v64.5"
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||||
"brcm,brcmstb-ddr-phy"
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||||
- reg : the DDR PHY register range and length
|
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||||
Example:
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ddr-phy@6000 {
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compatible = "brcm,brcmstb-ddr-phy-v64.5";
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reg = <0x6000 0xc8>;
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};
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== DDR memory controller sequencer
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||||
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Control registers for this memory controller's DDR memory sequencer
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one of these
|
||||
"brcm,bcm7425-memc-ddr"
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"brcm,bcm7429-memc-ddr"
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"brcm,bcm7435-memc-ddr" and
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"brcm,brcmstb-memc-ddr"
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- reg : the DDR sequencer register range and length
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||||
Example:
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memc-ddr@2000 {
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compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
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reg = <0x2000 0x300>;
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};
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== MEMC Arbiter
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The memory controller arbiter is responsible for memory clients allocation
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||||
(bandwidth, priorities etc.) and needs to have its contents restored during
|
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deep sleep states (S3).
|
||||
|
||||
Required properties:
|
||||
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||||
- compatible : should contain one of these
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||||
"brcm,brcmstb-memc-arb-v10.0.0.0"
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"brcm,brcmstb-memc-arb"
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- reg : the DDR Arbiter register range and length
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||||
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||||
Example:
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memc-arb@1000 {
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compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
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reg = <0x1000 0x248>;
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};
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||||
== Timers
|
||||
|
||||
The Broadcom STB chips contain a timer block with several general purpose
|
||||
timers that can be used.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should contain one of:
|
||||
"brcm,bcm7425-timers"
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"brcm,bcm7429-timers"
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"brcm,bcm7435-timers and
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"brcm,brcmstb-timers"
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- reg : the timers register range
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- interrupts : the interrupt line for this timer block
|
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Example:
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timers: timer@4067c0 {
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compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
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reg = <0x4067c0 0x40>;
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interrupts = <&periph_intc 19>;
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};
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|
|
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|
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@ -0,0 +1,61 @@
|
|||
Amlogic Meson Power Controller
|
||||
==============================
|
||||
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||||
The Amlogic Meson SoCs embeds an internal Power domain controller.
|
||||
|
||||
VPU Power Domain
|
||||
----------------
|
||||
|
||||
The Video Processing Unit power domain is controlled by this power controller,
|
||||
but the domain requires some external resources to meet the correct power
|
||||
sequences.
|
||||
The bindings must respect the power domain bindings as described in the file
|
||||
power_domain.txt
|
||||
|
||||
Device Tree Bindings:
|
||||
---------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
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||||
- #power-domain-cells: should be 0
|
||||
- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
|
||||
- resets: phandles to the reset lines needed for this power demain sequence
|
||||
as described in ../reset/reset.txt
|
||||
- clocks: from common clock binding: handle to VPU and VAPB clocks
|
||||
- clock-names: from common clock binding: must contain "vpu", "vapb"
|
||||
corresponding to entry in the clocks property.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
|
||||
- reg: base address and size of the AO system control register space.
|
||||
|
||||
Example:
|
||||
-------
|
||||
|
||||
ao_sysctrl: sys-ctrl@0 {
|
||||
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
|
||||
reg = <0x0 0x0 0x0 0x100>;
|
||||
|
||||
pwrc_vpu: power-controller-vpu {
|
||||
compatible = "amlogic,meson-gx-pwrc-vpu";
|
||||
#power-domain-cells = <0>;
|
||||
amlogic,hhi-sysctrl = <&sysctrl>;
|
||||
resets = <&reset RESET_VIU>,
|
||||
<&reset RESET_VENC>,
|
||||
<&reset RESET_VCBUS>,
|
||||
<&reset RESET_BT656>,
|
||||
<&reset RESET_DVIN_RESET>,
|
||||
<&reset RESET_RDMA>,
|
||||
<&reset RESET_VENCI>,
|
||||
<&reset RESET_VENCP>,
|
||||
<&reset RESET_VDAC>,
|
||||
<&reset RESET_VDI6>,
|
||||
<&reset RESET_VENCL>,
|
||||
<&reset RESET_VID_LOCK>;
|
||||
clocks = <&clkc CLKID_VPU>,
|
||||
<&clkc CLKID_VAPB>;
|
||||
clock-names = "vpu", "vapb";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -17,6 +17,7 @@ Required properties:
|
|||
- "renesas,r8a7794-sysc" (R-Car E2)
|
||||
- "renesas,r8a7795-sysc" (R-Car H3)
|
||||
- "renesas,r8a7796-sysc" (R-Car M3-W)
|
||||
- "renesas,r8a77970-sysc" (R-Car V3M)
|
||||
- "renesas,r8a77995-sysc" (R-Car D3)
|
||||
- reg: Address start and address range for the device.
|
||||
- #power-domain-cells: Must be 1.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
Qualcomm Remote File System Memory binding
|
||||
|
||||
This binding describes the Qualcomm remote filesystem memory, which serves the
|
||||
purpose of describing the shared memory region used for remote processors to
|
||||
access block device data using the Remote Filesystem protocol.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be:
|
||||
"qcom,rmtfs-mem"
|
||||
|
||||
- reg:
|
||||
Usage: required for static allocation
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify base address and size of the memory region,
|
||||
as described in reserved-memory.txt
|
||||
|
||||
- size:
|
||||
Usage: required for dynamic allocation
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: must specify a size of the memory region, as described in
|
||||
reserved-memory.txt
|
||||
|
||||
- qcom,client-id:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: identifier of the client to use this region for buffers.
|
||||
|
||||
- qcom,vmid:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: vmid of the remote processor, to set up memory protection.
|
||||
|
||||
= EXAMPLE
|
||||
The following example shows the remote filesystem memory setup for APQ8016,
|
||||
with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000.
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
rmtfs@86700000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
reg = <0x0 0x86700000 0x0 0xe0000>;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -26,6 +26,7 @@ Required properties:
|
|||
- "renesas,r8a7794-rst" (R-Car E2)
|
||||
- "renesas,r8a7795-rst" (R-Car H3)
|
||||
- "renesas,r8a7796-rst" (R-Car M3-W)
|
||||
- "renesas,r8a77970-rst" (R-Car V3M)
|
||||
- "renesas,r8a77995-rst" (R-Car D3)
|
||||
- reg: Address start and address range for the device.
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
Binding for the AXS10x reset controller
|
||||
|
||||
This binding describes the ARC AXS10x boards custom IP-block which allows
|
||||
to control reset signals of selected peripherals. For example DW GMAC, etc...
|
||||
This block is controlled via memory-mapped register (AKA CREG) which
|
||||
represents up-to 32 reset lines.
|
||||
|
||||
As of today only the following lines are used:
|
||||
- DW GMAC - line 5
|
||||
|
||||
This binding uses the common reset binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "snps,axs10x-reset".
|
||||
- reg: should always contain pair address - length: for creg reset
|
||||
bits register.
|
||||
- #reset-cells: from common reset binding; Should always be set to 1.
|
||||
|
||||
Example:
|
||||
reset: reset-controller@11220 {
|
||||
compatible = "snps,axs10x-reset";
|
||||
#reset-cells = <1>;
|
||||
reg = <0x11220 0x4>;
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules:
|
||||
ethernet@.... {
|
||||
....
|
||||
resets = <&reset 5>;
|
||||
....
|
||||
};
|
||||
|
|
@ -13,6 +13,7 @@ Required properties:
|
|||
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
|
||||
"socionext,uniphier-ld11-reset" - for LD11 SoC
|
||||
"socionext,uniphier-ld20-reset" - for LD20 SoC
|
||||
"socionext,uniphier-pxs3-reset" - for PXs3 SoC
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
|
@ -44,6 +45,7 @@ Required properties:
|
|||
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
|
||||
"socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
|
||||
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC
|
||||
"socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
|
@ -74,6 +76,7 @@ Required properties:
|
|||
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
|
||||
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC
|
||||
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC
|
||||
"socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
|
|
|||
|
|
@ -65,8 +65,8 @@ to the respective BMan instance
|
|||
BMan Private Memory Node
|
||||
|
||||
BMan requires a contiguous range of physical memory used for the backing store
|
||||
for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a
|
||||
node under the /reserved-memory node
|
||||
for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
|
||||
a node under the /reserved-memory node.
|
||||
|
||||
The BMan FBPR memory node must be named "bman-fbpr"
|
||||
|
||||
|
|
@ -75,7 +75,9 @@ PROPERTIES
|
|||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must inclide "fsl,bman-fbpr"
|
||||
Definition: PPC platforms: Must include "fsl,bman-fbpr"
|
||||
ARM platforms: Must include "shared-dma-pool"
|
||||
as well as the "no-map" property
|
||||
|
||||
The following constraints are relevant to the FBPR private memory:
|
||||
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
|
||||
|
|
@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation memory node
|
|||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "fsl,bman-fbpr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
compatible = "shared-mem-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
|
|||
Value type: <prop-encoded-array>
|
||||
Definition: Reference input clock. Its frequency is half of the
|
||||
platform clock
|
||||
- memory-regions
|
||||
Usage: Required for ARM
|
||||
Value type: <phandle array>
|
||||
Definition: List of phandles referencing the QMan private memory
|
||||
nodes (described below). The qman-fqd node must be
|
||||
first followed by qman-pfdr node. Only used on ARM
|
||||
|
||||
Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
|
||||
to the respective QMan instance
|
||||
|
|
@ -74,7 +80,9 @@ QMan Private Memory Nodes
|
|||
|
||||
QMan requires two contiguous range of physical memory used for the backing store
|
||||
for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
|
||||
This memory is reserved/allocated as a nodes under the /reserved-memory node
|
||||
This memory is reserved/allocated as a node under the /reserved-memory node.
|
||||
|
||||
For additional details about reserved memory regions see reserved-memory.txt
|
||||
|
||||
The QMan FQD memory node must be named "qman-fqd"
|
||||
|
||||
|
|
@ -83,7 +91,9 @@ PROPERTIES
|
|||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must inclide "fsl,qman-fqd"
|
||||
Definition: PPC platforms: Must include "fsl,qman-fqd"
|
||||
ARM platforms: Must include "shared-dma-pool"
|
||||
as well as the "no-map" property
|
||||
|
||||
The QMan PFDR memory node must be named "qman-pfdr"
|
||||
|
||||
|
|
@ -92,7 +102,9 @@ PROPERTIES
|
|||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must inclide "fsl,qman-pfdr"
|
||||
Definition: PPC platforms: Must include "fsl,qman-pfdr"
|
||||
ARM platforms: Must include "shared-dma-pool"
|
||||
as well as the "no-map" property
|
||||
|
||||
The following constraints are relevant to the FQD and PFDR private memory:
|
||||
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
|
||||
|
|
@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
|
|||
ranges;
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10 0>;
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ IP Pairing
|
|||
Required properties in pwrap device node.
|
||||
- compatible:
|
||||
"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
|
||||
"mediatek,mt7622-pwrap" for MT7622 SoCs
|
||||
"mediatek,mt8135-pwrap" for MT8135 SoCs
|
||||
"mediatek,mt8173-pwrap" for MT8173 SoCs
|
||||
- interrupts: IRQ for pwrap in SOC
|
||||
|
|
@ -36,9 +37,12 @@ Required properties in pwrap device node.
|
|||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
|
||||
Optional properities:
|
||||
- pmic: Mediatek PMIC MFD is the child device of pwrap
|
||||
- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
|
||||
See the following for child node definitions:
|
||||
Documentation/devicetree/bindings/mfd/mt6397.txt
|
||||
or the regulator-only device as the child device of pwrap, such as MT6380.
|
||||
See the following definitions for such kinds of devices.
|
||||
Documentation/devicetree/bindings/regulator/mt6380-regulator.txt
|
||||
|
||||
Example:
|
||||
pwrap: pwrap@1000f000 {
|
||||
|
|
|
|||
Loading…
Reference in a new issue