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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 23:24:22 -04:00
msm: kgsl: Remove unneeded static inline functions
Over the years we have really abused inline functions in the driver code. Remove a chunk of the "functions" that are single use or otherwise just not worth it. As a bonus, moving the functions around exposed a single use of some adreno_reg registers in a3xx that we could get rid of that while we are mucking about. Change-Id: Ic0dedbad85df436cbd7e5746964200ee9f87e1a4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse
parent
41b90d7bcd
commit
cfa7f9cf2a
12 changed files with 103 additions and 237 deletions
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@ -168,22 +168,6 @@ unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb)
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return rptr;
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}
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/**
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* adreno_of_read_property() - Adreno read property
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* @node: Device node
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*
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* Read a u32 property.
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*/
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static inline int adreno_of_read_property(struct device *dev,
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struct device_node *node, const char *prop, unsigned int *ptr)
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{
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int ret = of_property_read_u32(node, prop, ptr);
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if (ret)
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dev_err(dev, "%pOF: Unable to read '%s'\n", node, prop);
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return ret;
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}
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static void __iomem *efuse_base;
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static size_t efuse_len;
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@ -259,18 +243,6 @@ static int _get_counter(struct adreno_device *adreno_dev,
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return ret;
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}
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static inline void _put_counter(struct adreno_device *adreno_dev,
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int group, int countable, unsigned int *lo,
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unsigned int *hi)
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{
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if (*lo != 0)
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adreno_perfcounter_put(adreno_dev, group, countable,
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PERFCOUNTER_FLAG_KERNEL);
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*lo = 0;
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*hi = 0;
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}
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/**
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* adreno_fault_detect_start() - Allocate performance counters
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* used for fast fault detection
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@ -319,11 +291,16 @@ void adreno_fault_detect_stop(struct adreno_device *adreno_dev)
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return;
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for (i = 0; i < gpudev->ft_perf_counters_count; i++) {
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_put_counter(adreno_dev, gpudev->ft_perf_counters[i].counter,
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gpudev->ft_perf_counters[i].countable,
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&adreno_ft_regs[j + (i * 2)],
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&adreno_ft_regs[j + ((i * 2) + 1)]);
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if (!adreno_ft_regs[j + (i * 2)])
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continue;
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adreno_perfcounter_put(adreno_dev,
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gpudev->ft_perf_counters[i].counter,
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gpudev->ft_perf_counters[i].countable,
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PERFCOUNTER_FLAG_KERNEL);
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adreno_ft_regs[j + (i * 2)] = 0;
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adreno_ft_regs[(j + (i * 2)) + 1] = 0;
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}
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adreno_dev->fast_hang_detect = 0;
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@ -921,8 +898,11 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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unsigned int index;
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struct kgsl_pwrlevel *level;
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if (adreno_of_read_property(device->dev, child, "reg", &index))
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if (of_property_read_u32(child, "reg", &index)) {
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dev_err(device->dev,
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"%pOF: powerlevel index not found\n", child);
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return -EINVAL;
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}
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if (index >= KGSL_MAX_PWRLEVELS) {
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dev_err(device->dev,
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@ -936,9 +916,12 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
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level = &pwr->pwrlevels[index];
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if (adreno_of_read_property(device->dev, child, "qcom,gpu-freq",
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&level->gpu_freq))
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if (of_property_read_u32(child, "qcom,gpu-freq",
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&level->gpu_freq)) {
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dev_err(device->dev,
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"%pOF: Unable to read qcom,gpu-freq\n", child);
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return -EINVAL;
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}
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of_property_read_u32(child, "qcom,acd-level",
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&level->acd_level);
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@ -2227,27 +2210,6 @@ static int adreno_stop(struct kgsl_device *device)
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return error;
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}
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static inline bool adreno_try_soft_reset(struct kgsl_device *device, int fault)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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/*
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* Do not do soft reset for a IOMMU fault (because the IOMMU hardware
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* needs a reset too) and also for below gpu
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* A304: It can't do SMMU programming of any kind after a soft reset
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* A612: IPC protocol between RGMU and CP will not restart after reset
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* A610: An across chip issue with reset line in all 11nm chips,
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* resulting in recommendation to not use soft reset
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*/
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if ((fault & ADRENO_IOMMU_PAGE_FAULT) || adreno_is_a304(adreno_dev) ||
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adreno_is_a612(adreno_dev) ||
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adreno_is_a610(adreno_dev))
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return false;
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return true;
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}
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/**
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* adreno_reset() - Helper function to reset the GPU
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* @device: Pointer to the KGSL device structure for the GPU
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@ -2263,8 +2225,14 @@ int adreno_reset(struct kgsl_device *device, int fault)
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int ret = -EINVAL;
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int i = 0;
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/* Try soft reset first */
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if (adreno_try_soft_reset(device, fault)) {
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/*
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* Try soft reset first Do not do soft reset for a IOMMU fault (because
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* the IOMMU hardware needs a reset too) or for the A304 because it
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* can't do SMMU programming of any kind after a soft reset
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*/
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if (!(fault & ADRENO_IOMMU_PAGE_FAULT) && !adreno_is_a304(adreno_dev)
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&& !adreno_is_a612(adreno_dev) && !adreno_is_a610(adreno_dev)) {
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/* Make sure VBIF is cleared before resetting */
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ret = adreno_clear_pending_transactions(device);
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@ -3514,12 +3482,6 @@ static void adreno_device_private_destroy(struct kgsl_device_private *dev_priv)
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kfree(adreno_priv);
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}
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static inline s64 adreno_ticks_to_us(u32 ticks, u32 freq)
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{
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freq /= 1000000;
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return ticks / freq;
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}
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/**
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* adreno_power_stats() - Reads the counters needed for freq decisions
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* @device: Pointer to device whose counters are read
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@ -3556,8 +3518,9 @@ static void adreno_power_stats(struct kgsl_device *device,
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do_div(stats->busy_time, 192);
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} else {
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/* clock sourced from GFX3D */
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stats->busy_time = adreno_ticks_to_us(gpu_busy,
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kgsl_pwrctrl_active_freq(pwr));
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s64 freq = kgsl_pwrctrl_active_freq(pwr) / 1000000;
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stats->busy_time = gpu_busy / freq;
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}
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if (device->pwrctrl.bus_control) {
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@ -594,10 +594,7 @@ struct adreno_drawobj_profile_entry {
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* and are indexed by the enumeration values defined in this enum
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*/
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enum adreno_regs {
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ADRENO_REG_CP_ME_RAM_WADDR,
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ADRENO_REG_CP_ME_RAM_DATA,
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ADRENO_REG_CP_PFP_UCODE_DATA,
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ADRENO_REG_CP_PFP_UCODE_ADDR,
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ADRENO_REG_CP_RB_BASE,
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ADRENO_REG_CP_RB_BASE_HI,
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ADRENO_REG_CP_RB_RPTR_ADDR_LO,
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@ -616,7 +613,6 @@ enum adreno_regs {
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ADRENO_REG_CP_TIMESTAMP,
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ADRENO_REG_CP_SCRATCH_REG6,
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ADRENO_REG_CP_SCRATCH_REG7,
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ADRENO_REG_CP_ME_RAM_RADDR,
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ADRENO_REG_CP_ROQ_ADDR,
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ADRENO_REG_CP_ROQ_DATA,
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ADRENO_REG_CP_MEQ_ADDR,
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@ -660,12 +660,11 @@ static int a3xx_send_me_init(struct adreno_device *adreno_dev,
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return ret;
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}
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static int a3xx_microcode_load(struct adreno_device *adreno_dev);
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static void a3xx_microcode_load(struct adreno_device *adreno_dev);
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static int a3xx_rb_start(struct adreno_device *adreno_dev)
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{
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struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev);
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int ret;
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/*
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* The size of the ringbuffer in the hardware is the log2
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@ -681,15 +680,12 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev)
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adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,
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rb->buffer_desc.gpuaddr);
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ret = a3xx_microcode_load(adreno_dev);
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if (ret == 0) {
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/* clear ME_HALT to start micro engine */
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adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);
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a3xx_microcode_load(adreno_dev);
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ret = a3xx_send_me_init(adreno_dev, rb);
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}
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/* clear ME_HALT to start micro engine */
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adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, 0);
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return ret;
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return a3xx_send_me_init(adreno_dev, rb);
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}
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/*
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@ -1200,10 +1196,6 @@ static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = {
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/* Register offset defines for A3XX */
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static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_WADDR, A3XX_CP_ME_RAM_WADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_DATA, A3XX_CP_ME_RAM_DATA),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_DATA, A3XX_CP_PFP_UCODE_DATA),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_PFP_UCODE_ADDR, A3XX_CP_PFP_UCODE_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A3XX_CP_RB_BASE),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, ADRENO_REG_SKIP),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A3XX_CP_RB_RPTR),
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@ -1220,7 +1212,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
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ADRENO_REG_DEFINE(ADRENO_REG_CP_TIMESTAMP, A3XX_CP_SCRATCH_REG0),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG6, A3XX_CP_SCRATCH_REG6),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG7, A3XX_CP_SCRATCH_REG7),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_RAM_RADDR, A3XX_CP_ME_RAM_RADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A3XX_CP_ROQ_ADDR),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A3XX_CP_ROQ_DATA),
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ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A3XX_CP_MEQ_ADDR),
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@ -1355,57 +1346,25 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev)
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return 0;
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}
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/**
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* load_pm4_ucode() - Load pm4 ucode
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* @adreno_dev: Pointer to an adreno device
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* @start: Starting index in pm4 ucode to load
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* @end: Ending index of pm4 ucode to load
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* @addr: Address to load the pm4 ucode
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*
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* Load the pm4 ucode from @start at @addr.
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*/
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static inline void load_pm4_ucode(struct adreno_device *adreno_dev,
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unsigned int start, unsigned int end, unsigned int addr)
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{
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int i;
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adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_RAM_WADDR, addr);
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for (i = start; i < end; i++)
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adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_RAM_DATA,
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adreno_dev->fw[ADRENO_FW_PM4].fwvirt[i]);
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}
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/**
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* load_pfp_ucode() - Load pfp ucode
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* @adreno_dev: Pointer to an adreno device
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* @start: Starting index in pfp ucode to load
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* @end: Ending index of pfp ucode to load
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* @addr: Address to load the pfp ucode
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*
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* Load the pfp ucode from @start at @addr.
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*/
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static inline void load_pfp_ucode(struct adreno_device *adreno_dev,
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unsigned int start, unsigned int end, unsigned int addr)
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{
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int i;
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adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_ADDR, addr);
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for (i = start; i < end; i++)
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adreno_writereg(adreno_dev, ADRENO_REG_CP_PFP_UCODE_DATA,
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adreno_dev->fw[ADRENO_FW_PFP].fwvirt[i]);
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}
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static int a3xx_microcode_load(struct adreno_device *adreno_dev)
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static void a3xx_microcode_load(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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size_t pm4_size = adreno_dev->fw[ADRENO_FW_PM4].size;
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size_t pfp_size = adreno_dev->fw[ADRENO_FW_PFP].size;
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int i;
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/* load the CP ucode using AHB writes */
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load_pm4_ucode(adreno_dev, 1, pm4_size, 0);
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kgsl_regwrite(device, A3XX_CP_ME_RAM_WADDR, 0);
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/* load the prefetch parser ucode using AHB writes */
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load_pfp_ucode(adreno_dev, 1, pfp_size, 0);
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for (i = 1; i < pm4_size; i++)
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kgsl_regwrite(device, A3XX_CP_ME_RAM_DATA,
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adreno_dev->fw[ADRENO_FW_PM4].fwvirt[i]);
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return 0;
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kgsl_regwrite(device, A3XX_CP_PFP_UCODE_ADDR, 0);
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for (i = 1; i < pfp_size; i++)
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kgsl_regwrite(device, A3XX_CP_PFP_UCODE_DATA,
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adreno_dev->fw[ADRENO_FW_PFP].fwvirt[i]);
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}
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static void a3xx_clk_set_options(struct adreno_device *adreno_dev,
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@ -938,7 +938,7 @@ static int _load_firmware(struct kgsl_device *device, const char *fwfile,
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* @adreno_dev: Pointer to the adreno device that has the GMU
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* @state: State to set: true is ON, false is OFF
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*/
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static inline void a6xx_gpu_keepalive(struct adreno_device *adreno_dev,
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static void a6xx_gpu_keepalive(struct adreno_device *adreno_dev,
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bool state)
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{
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if (!gmu_core_isenabled(KGSL_DEVICE(adreno_dev)))
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@ -609,7 +609,7 @@ static int a6xx_gmu_oob_set(struct kgsl_device *device,
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* @device: Pointer to the kgsl device that has the GMU
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* @req: Which of the OOB bits to clear
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*/
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static inline void a6xx_gmu_oob_clear(struct kgsl_device *device,
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static void a6xx_gmu_oob_clear(struct kgsl_device *device,
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enum oob_request req)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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@ -130,7 +130,7 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device,
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* @adreno_dev: Pointer to the adreno device that has the RGMU
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* @req: Which of the OOB bits to clear
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*/
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static inline void a6xx_rgmu_oob_clear(struct kgsl_device *device,
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static void a6xx_rgmu_oob_clear(struct kgsl_device *device,
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enum oob_request req)
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{
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gmu_core_regwrite(device, A6XX_GMU_HOST2GMU_INTR_SET, BIT(req + 24));
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@ -295,27 +295,8 @@ void adreno_drawctxt_invalidate(struct kgsl_device *device,
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wake_up_all(&drawctxt->timeout);
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}
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/*
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* Set the priority of the context based on the flags passed into context
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* create. If the priority is not set in the flags, then the kernel can
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* assign any priority it desires for the context.
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*/
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#define KGSL_CONTEXT_PRIORITY_MED 0x8
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static inline void _set_context_priority(struct adreno_context *drawctxt)
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{
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/* If the priority is not set by user, set it for them */
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if ((drawctxt->base.flags & KGSL_CONTEXT_PRIORITY_MASK) ==
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KGSL_CONTEXT_PRIORITY_UNDEF)
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drawctxt->base.flags |= (KGSL_CONTEXT_PRIORITY_MED <<
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KGSL_CONTEXT_PRIORITY_SHIFT);
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/* Store the context priority */
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drawctxt->base.priority =
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(drawctxt->base.flags & KGSL_CONTEXT_PRIORITY_MASK) >>
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KGSL_CONTEXT_PRIORITY_SHIFT;
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}
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/**
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* adreno_drawctxt_create - create a new adreno draw context
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* @dev_priv: the owner of the context
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@ -389,8 +370,17 @@ adreno_drawctxt_create(struct kgsl_device_private *dev_priv,
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init_waitqueue_head(&drawctxt->waiting);
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init_waitqueue_head(&drawctxt->timeout);
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/* Set the context priority */
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_set_context_priority(drawctxt);
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/* If the priority is not set by user, set it for them */
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if ((drawctxt->base.flags & KGSL_CONTEXT_PRIORITY_MASK) ==
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KGSL_CONTEXT_PRIORITY_UNDEF)
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drawctxt->base.flags |= (KGSL_CONTEXT_PRIORITY_MED <<
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KGSL_CONTEXT_PRIORITY_SHIFT);
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/* Store the context priority */
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drawctxt->base.priority =
|
||||
(drawctxt->base.flags & KGSL_CONTEXT_PRIORITY_MASK) >>
|
||||
KGSL_CONTEXT_PRIORITY_SHIFT;
|
||||
|
||||
/* set the context ringbuffer */
|
||||
drawctxt->rb = adreno_ctx_get_rb(adreno_dev, drawctxt);
|
||||
|
||||
|
|
|
|||
|
|
@ -168,25 +168,6 @@ static unsigned int adreno_iommu_set_apriv(struct adreno_device *adreno_dev,
|
|||
return cmds - cmds_orig;
|
||||
}
|
||||
|
||||
static inline int _adreno_iommu_add_idle_indirect_cmds(
|
||||
struct adreno_device *adreno_dev,
|
||||
unsigned int *cmds, uint64_t nop_gpuaddr)
|
||||
{
|
||||
unsigned int *start = cmds;
|
||||
/*
|
||||
* Adding an indirect buffer ensures that the prefetch stalls until
|
||||
* the commands in indirect buffer have completed. We need to stall
|
||||
* prefetch with a nop indirect buffer when updating pagetables
|
||||
* because it provides stabler synchronization.
|
||||
*/
|
||||
cmds += cp_wait_for_me(adreno_dev, cmds);
|
||||
*cmds++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1);
|
||||
cmds += cp_gpuaddr(adreno_dev, cmds, nop_gpuaddr);
|
||||
*cmds++ = 2;
|
||||
cmds += cp_wait_for_idle(adreno_dev, cmds);
|
||||
return cmds - start;
|
||||
}
|
||||
|
||||
static unsigned int _adreno_iommu_set_pt_v2_a3xx(struct kgsl_device *device,
|
||||
unsigned int *cmds_orig,
|
||||
u64 ttbr0, u32 contextidr)
|
||||
|
|
@ -306,9 +287,18 @@ unsigned int adreno_iommu_set_pt_generate_cmds(
|
|||
contextidr = kgsl_mmu_pagetable_get_contextidr(pt);
|
||||
|
||||
cmds += adreno_iommu_set_apriv(adreno_dev, cmds, 1);
|
||||
|
||||
cmds += _adreno_iommu_add_idle_indirect_cmds(adreno_dev, cmds,
|
||||
/*
|
||||
* Adding an indirect buffer ensures that the prefetch stalls until
|
||||
* the commands in indirect buffer have completed. We need to stall
|
||||
* prefetch with a nop indirect buffer when updating pagetables
|
||||
* because it provides stabler synchronization.
|
||||
*/
|
||||
cmds += cp_wait_for_me(adreno_dev, cmds);
|
||||
*cmds++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1);
|
||||
cmds += cp_gpuaddr(adreno_dev, cmds,
|
||||
iommu->setstate.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET);
|
||||
*cmds++ = 2;
|
||||
cmds += cp_wait_for_idle(adreno_dev, cmds);
|
||||
|
||||
if (adreno_is_a6xx(adreno_dev))
|
||||
cmds += _adreno_iommu_set_pt_v2_a6xx(device, cmds,
|
||||
|
|
|
|||
|
|
@ -224,17 +224,6 @@ static void drawobj_sync_func(struct kgsl_device *device,
|
|||
kgsl_drawobj_put(&event->syncobj->base);
|
||||
}
|
||||
|
||||
static inline void memobj_list_free(struct list_head *list)
|
||||
{
|
||||
struct kgsl_memobj_node *mem, *tmpmem;
|
||||
|
||||
/* Free the cmd mem here */
|
||||
list_for_each_entry_safe(mem, tmpmem, list, node) {
|
||||
list_del_init(&mem->node);
|
||||
kmem_cache_free(memobjs_cache, mem);
|
||||
}
|
||||
}
|
||||
|
||||
static void drawobj_destroy_sparse(struct kgsl_drawobj *drawobj)
|
||||
{
|
||||
struct kgsl_sparseobj_node *mem, *tmpmem;
|
||||
|
|
@ -302,6 +291,7 @@ static void drawobj_destroy_sync(struct kgsl_drawobj *drawobj)
|
|||
static void drawobj_destroy_cmd(struct kgsl_drawobj *drawobj)
|
||||
{
|
||||
struct kgsl_drawobj_cmd *cmdobj = CMDOBJ(drawobj);
|
||||
struct kgsl_memobj_node *mem, *tmpmem;
|
||||
|
||||
/*
|
||||
* Release the refcount on the mem entry associated with the
|
||||
|
|
@ -310,11 +300,17 @@ static void drawobj_destroy_cmd(struct kgsl_drawobj *drawobj)
|
|||
if (cmdobj->base.flags & KGSL_DRAWOBJ_PROFILING)
|
||||
kgsl_mem_entry_put(cmdobj->profiling_buf_entry);
|
||||
|
||||
/* Destroy the cmdlist we created */
|
||||
memobj_list_free(&cmdobj->cmdlist);
|
||||
/* Destroy the command list */
|
||||
list_for_each_entry_safe(mem, tmpmem, &cmdobj->cmdlist, node) {
|
||||
list_del_init(&mem->node);
|
||||
kmem_cache_free(memobjs_cache, mem);
|
||||
}
|
||||
|
||||
/* Destroy the memlist we created */
|
||||
memobj_list_free(&cmdobj->memlist);
|
||||
/* Destroy the memory list */
|
||||
list_for_each_entry_safe(mem, tmpmem, &cmdobj->memlist, node) {
|
||||
list_del_init(&mem->node);
|
||||
kmem_cache_free(memobjs_cache, mem);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -32,12 +32,6 @@ static void kgsl_destroy_pagetable(struct kref *kref)
|
|||
kgsl_schedule_work(&pagetable->destroy_ws);
|
||||
}
|
||||
|
||||
static inline void kgsl_put_pagetable(struct kgsl_pagetable *pagetable)
|
||||
{
|
||||
if (pagetable)
|
||||
kref_put(&pagetable->refcount, kgsl_destroy_pagetable);
|
||||
}
|
||||
|
||||
struct kgsl_pagetable *
|
||||
kgsl_get_pagetable(unsigned long name)
|
||||
{
|
||||
|
|
@ -86,7 +80,7 @@ sysfs_show_entries(struct kobject *kobj,
|
|||
ret += scnprintf(buf, PAGE_SIZE, "%d\n", val);
|
||||
}
|
||||
|
||||
kgsl_put_pagetable(pt);
|
||||
kref_put(&pt->refcount, kgsl_destroy_pagetable);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -106,7 +100,7 @@ sysfs_show_mapped(struct kobject *kobj,
|
|||
ret += scnprintf(buf, PAGE_SIZE, "%llu\n", val);
|
||||
}
|
||||
|
||||
kgsl_put_pagetable(pt);
|
||||
kref_put(&pt->refcount, kgsl_destroy_pagetable);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -126,7 +120,7 @@ sysfs_show_max_mapped(struct kobject *kobj,
|
|||
ret += scnprintf(buf, PAGE_SIZE, "%llu\n", val);
|
||||
}
|
||||
|
||||
kgsl_put_pagetable(pt);
|
||||
kref_put(&pt->refcount, kgsl_destroy_pagetable);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -307,7 +301,8 @@ kgsl_mmu_createpagetableobject(struct kgsl_mmu *mmu, unsigned int name)
|
|||
|
||||
void kgsl_mmu_putpagetable(struct kgsl_pagetable *pagetable)
|
||||
{
|
||||
kgsl_put_pagetable(pagetable);
|
||||
if (pagetable)
|
||||
kref_put(&pagetable->refcount, kgsl_destroy_pagetable);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1589,18 +1589,6 @@ static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline void _close_clks(struct kgsl_device *device)
|
||||
{
|
||||
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < KGSL_MAX_CLKS; i++)
|
||||
pwr->grp_clks[i] = NULL;
|
||||
|
||||
if (pwr->gpu_bimc_int_clk)
|
||||
devm_clk_put(&device->pdev->dev, pwr->gpu_bimc_int_clk);
|
||||
}
|
||||
|
||||
static bool _gpu_freq_supported(struct kgsl_pwrctrl *pwr, unsigned int freq)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1674,7 +1662,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
|
|||
|
||||
result = _get_clocks(device);
|
||||
if (result)
|
||||
goto error_cleanup_clks;
|
||||
return result;
|
||||
|
||||
/* Make sure we have a source clk for freq setting */
|
||||
if (pwr->grp_clks[0] == NULL)
|
||||
|
|
@ -1692,8 +1680,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
|
|||
|
||||
if (pwr->num_pwrlevels == 0) {
|
||||
dev_err(device->dev, "No power levels are defined\n");
|
||||
result = -EINVAL;
|
||||
goto error_cleanup_clks;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Initialize the user and thermal clock constraints */
|
||||
|
|
@ -1785,9 +1772,8 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
|
|||
|
||||
error_disable_pm:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
error_cleanup_clks:
|
||||
_close_clks(device);
|
||||
kfree(levels);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -1802,8 +1788,6 @@ void kgsl_pwrctrl_close(struct kgsl_device *device)
|
|||
icc_put(pwr->icc_path);
|
||||
|
||||
pm_runtime_disable(&device->pdev->dev);
|
||||
|
||||
_close_clks(device);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -109,18 +109,6 @@ static int rgmu_clocks_probe(struct rgmu_device *rgmu, struct device_node *node)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline int rgmu_clk_set_rate(struct clk *grp_clk, unsigned int freq)
|
||||
{
|
||||
int ret = clk_set_rate(grp_clk, freq);
|
||||
|
||||
if (ret)
|
||||
pr_err("%s set freq %d failed:%d\n",
|
||||
__clk_get_name(grp_clk), freq, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void rgmu_disable_clks(struct kgsl_device *device)
|
||||
{
|
||||
struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);
|
||||
|
|
@ -168,16 +156,18 @@ static int rgmu_enable_clks(struct kgsl_device *device)
|
|||
IS_ERR_OR_NULL(rgmu->gpu_clk))
|
||||
return -EINVAL;
|
||||
|
||||
/* Let us set rgmu clk */
|
||||
ret = rgmu_clk_set_rate(rgmu->rgmu_clk, RGMU_CLK_FREQ);
|
||||
if (ret)
|
||||
ret = clk_set_rate(rgmu->rgmu_clk, RGMU_CLK_FREQ);
|
||||
if (ret) {
|
||||
dev_err(&rgmu->pdev->dev, "Couldn't set the RGMU clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Let us set gpu clk to default power level */
|
||||
ret = rgmu_clk_set_rate(rgmu->gpu_clk,
|
||||
rgmu->gpu_freqs[pwr->default_pwrlevel]);
|
||||
if (ret)
|
||||
ret = clk_set_rate(rgmu->gpu_clk,
|
||||
rgmu->gpu_freqs[pwr->default_pwrlevel]);
|
||||
if (ret) {
|
||||
dev_err(&rgmu->pdev->dev, "Couldn't set the GPU clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (j = 0; j < ARRAY_SIZE(rgmu->clks); j++) {
|
||||
ret = clk_prepare_enable(rgmu->clks[j]);
|
||||
|
|
@ -430,13 +420,16 @@ static int rgmu_dcvs_set(struct kgsl_device *device,
|
|||
unsigned int pwrlevel, unsigned int bus_level)
|
||||
{
|
||||
struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);
|
||||
int ret;
|
||||
|
||||
if (pwrlevel == INVALID_DCVS_IDX)
|
||||
return -EINVAL;
|
||||
|
||||
return rgmu_clk_set_rate(rgmu->gpu_clk,
|
||||
rgmu->gpu_freqs[pwrlevel]);
|
||||
ret = clk_set_rate(rgmu->gpu_clk, rgmu->gpu_freqs[pwrlevel]);
|
||||
if (ret)
|
||||
dev_err(&rgmu->pdev->dev, "Couldn't set the GPU clock\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool rgmu_regulator_isenabled(struct kgsl_device *device)
|
||||
|
|
|
|||
Loading…
Reference in a new issue