From 64d66d86566a4b325aeecec2f23cd2258be24a35 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:41:26 +0800 Subject: [PATCH 1/3] ARM: dts: msm: update clock entries to support CPHY for Lahaina Add cphy specific clock entries for both the DSI controller nodes. Change-Id: I9694595cc079249ad2e4ed58d353f0cc8e3692e4 --- display/lahaina-sde-display.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 47efdcc7d8e4..0008a22e9303 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -132,10 +132,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -163,10 +169,16 @@ clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, + <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, + <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>; + <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, + <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, + <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1"; + "cphy_byte_clk0", "cphy_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; From 932e556bf17e95922fff659698e0f78370a31e4d Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 15:48:10 +0800 Subject: [PATCH 2/3] dt-bindings: add new property to specify PHY type Add new boolean property that specifies whether the panel is using DSI CPHY. If this property is not set, default PHY type i.e. DPHY will be used. Change-Id: I82e1738e64027e74a7752996c28b10ebdfdf3e15 --- bindings/mdss-dsi-panel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 3810bb221e3a..73cf79d6611e 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -504,7 +504,7 @@ Optional properties: - qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel for any commands that we send. - qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. - +- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. - qcom,compression-mode: Select compression mode for panel. "fbc" - frame buffer compression "dsc" - display stream compression. From 4b64e529ee5d2c0982f44530fa8cb80d43cecba4 Mon Sep 17 00:00:00 2001 From: Yuan Zhao Date: Sun, 19 Apr 2020 21:37:11 +0800 Subject: [PATCH 3/3] ARM: dts: msm: add r66451 cphy panel support for lahaina Add DDIC R66451 Visionox panel CPHY cmd and video mode support. Change-Id: I1952f26dd0437816a5f367f09c4664fb6420966c --- ...si-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi | 100 ++++++++++++++++++ ...-panel-r66451-dsc-fhd-plus-video-cphy.dtsi | 83 +++++++++++++++ display/lahaina-sde-display-cdp.dtsi | 19 ++++ display/lahaina-sde-display-mtp.dtsi | 19 ++++ display/lahaina-sde-display-qrd.dtsi | 19 ++++ display/lahaina-sde-display.dtsi | 28 +++++ 6 files changed, 268 insertions(+) create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi new file mode 100644 index 000000000000..8b540370ae41 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi @@ -0,0 +1,100 @@ +&mdss_mdp { + dsi_r66451_amoled_cmd_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_cmd { + qcom,mdss-dsi-panel-name = + "r66451 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-mdp-transfer-time-us = <15300>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 03 eb 00 00 + 39 01 00 00 00 00 02 f7 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 13 d8 00 00 00 00 00 + 00 00 00 00 5b 00 5b 00 5b 00 5b 00 + 5b + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi new file mode 100644 index 000000000000..4e898a61b030 --- /dev/null +++ b/display/dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi @@ -0,0 +1,83 @@ +&mdss_mdp { + dsi_r66451_amoled_video_cphy: qcom,mdss_dsi_r66451_fhd_plus_cphy_vid { + qcom,mdss-dsi-panel-name = + "r66451 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <96>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <32>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <25>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 02 b0 80 + 39 01 00 00 00 00 02 e6 00 + 39 01 00 00 00 00 02 b0 00 + 39 01 00 00 00 00 06 B6 6c 00 06 23 a6 + 39 01 00 00 00 00 02 B4 20 + 39 01 00 00 00 00 19 cf 64 0b 00 00 00 + 00 00 00 08 00 0b 77 01 01 01 01 01 + 01 04 04 04 04 04 05 + 39 01 00 00 00 00 02 b0 04 + 39 01 00 00 00 00 02 f7 01 + 39 01 00 00 00 00 03 df 50 40 + 39 01 00 00 00 00 06 f3 50 00 00 00 00 + 39 01 00 00 00 00 02 f2 11 + 39 01 00 00 00 00 06 f3 01 00 00 00 01 + 39 01 00 00 00 00 03 f4 00 02 + 39 01 00 00 00 00 02 f2 19 + 39 01 00 00 00 00 03 df 50 42 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 23 + 05 01 00 00 78 00 01 11 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/lahaina-sde-display-cdp.dtsi b/display/lahaina-sde-display-cdp.dtsi index 876780b10608..3597392d094b 100644 --- a/display/lahaina-sde-display-cdp.dtsi +++ b/display/lahaina-sde-display-cdp.dtsi @@ -41,6 +41,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-mtp.dtsi b/display/lahaina-sde-display-mtp.dtsi index 8594b9d3d0b5..67eab860d2d8 100644 --- a/display/lahaina-sde-display-mtp.dtsi +++ b/display/lahaina-sde-display-mtp.dtsi @@ -38,6 +38,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sharp_4k_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/lahaina-sde-display-qrd.dtsi b/display/lahaina-sde-display-qrd.dtsi index cee3ab009b04..913eb806336b 100644 --- a/display/lahaina-sde-display-qrd.dtsi +++ b/display/lahaina-sde-display-qrd.dtsi @@ -19,6 +19,25 @@ qcom,platform-reset-gpio = <&tlmm 24 0>; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 82 0>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 24 0>; +}; + &dsi_sw43404_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/lahaina-sde-display.dtsi b/display/lahaina-sde-display.dtsi index 0008a22e9303..a2a1caf972ab 100644 --- a/display/lahaina-sde-display.dtsi +++ b/display/lahaina-sde-display.dtsi @@ -13,6 +13,8 @@ #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-r66451-dsc-qhd-cmd.dtsi" #include "dsi-panel-r66451-dsc-qhd-video.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-video-cphy.dtsi" +#include "dsi-panel-r66451-dsc-fhd-plus-cmd-cphy.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" @@ -294,6 +296,32 @@ }; }; +&dsi_r66451_amoled_cmd_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_r66451_amoled_video_cphy { + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 04 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; qcom,esd-check-enabled;