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clk: qcom: gpucc: Update the PLL 2x frequency

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The GPUCC PLL needs to lock at 2x the RCG frequency, thus update the RCG
divider to '2' to lock the PLL at 2x.

Change-Id: Iadeb8b03cf10c170efa8b11bf9aadc35f67ce736
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2020-10-01 21:42:28 +05:30
commit d06d88cb08
1 changed files with 7 additions and 7 deletions
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14
drivers/clk/qcom/gpucc-holi.c
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@ -200,13 +200,13 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
F(253000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(355000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(430000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(565000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(800000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(875000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};