A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Define console before other QUP devices on shima"

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This commit is contained in:
qctecmdr 2020-08-18 04:33:27 -07:00 • committed by Gerrit - the friendly Code Review server
commit d0730cf0bd
1 changed files with 17 additions and 17 deletions
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34
qcom/shima-qupv3.dtsi
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@ -60,6 +60,23 @@
status = "ok"
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@994000 {
compatible = "qcom,msm-geni-console";
reg = <0x994000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok"
};
qupv3_se8_i2c: i2c@980000 {
compatible = "qcom,i2c-geni";
reg = <0x980000 0x4000>;
@ -270,23 +287,6 @@
status = "disabled";
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@994000 {
compatible = "qcom,msm-geni-console";
reg = <0x994000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok"
};
qupv3_se14_i2c: i2c@998000 {
compatible = "qcom,i2c-geni";
reg = <0x998000 0x4000>;