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Samsung cleanup for v3.20
- remove i2c sys configuration from mach-exynos/ : all related codes moved into i2c driver - remove Samsung specific DMA : every Samsung stuff uses dmaengine APIs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUyXM3AAoJEA0Cl+kVi2xqn8MP/jDl9Jgx94dvLoj+jZxrN/QL qm4ZbhWnQ+DCv6B8GSgkwljWTpQazqUztft1FXpjKUW3p2VoQHugb0a62jySx6vG VKCxLsZh95Zj7ZL1q18v1HO7zrAm/TdWl7H+j55jATfQVQGmHeiFTkyHBYVmicHU /HMwT3C42oJEiz58BPs0uoM5Pfm+2cV8J4yj2VMIQXLx5y52+Ic0s228yJxqWYuO Nm7RGMW5oJwkgAli2ug0VqMUYGVg4otiNqoXIl9DP1B+yhdvEsXrkPcDNvTqgJBU nq+ho3X2qFM+ETMi80QA4YNq/MM5Ns3cqwMprVTeAvMe8xJqjL3FpSc3eDQRRhHq LHn0eUhwOj4xWa5d/dku6Onp1UOBSqvuURj30Vg2OXMwwBa/DD5g3sihmvBXUdVa Bd8QEWl9gcVTXqjRb3V2X9UdID3EZMongAohzAqi/ailb8kFmdGPOt7EZsPGa4ZA YkxR/KvcLMEjClwGVDH9x7vJq8rONSi+zWhE3MbBMjyj4quUv4tzMUb2Bl2dkrma lrpberjceQ2gLIRFC8fy5JoL4sNfIT3JcCpLCRMZXK9SbWx7UjdV3Ni8m04ldwJt +Jjoh2qiZ/wsFH++RyJ2K3yrntcGhzqe/wfm1ZB6dGe0W/XRIOb/dq9vBODbX/9W yl99BuYWxUZw9aHPfRp2 =2/ZU -----END PGP SIGNATURE----- Merge tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup Merge "Samsung cleanup for v3.20" from Kukjin Kim: - remove i2c sys configuration from mach-exynos/ : all related codes moved into i2c driver - remove Samsung specific DMA : every Samsung stuff uses dmaengine APIs * tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: SAMSUNG: remove unused DMA infrastructure ARM: EXYNOS: Remove i2c sys configuration related code Signed-off-by: Olof Johansson <[email protected]>
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S3C2410 DMA
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===========
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Introduction
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------------
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The kernel provides an interface to manage DMA transfers
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using the DMA channels in the CPU, so that the central
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duty of managing channel mappings, and programming the
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channel generators is in one place.
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DMA Channel Ordering
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--------------------
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Many of the range do not have connections for the DMA
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channels to all sources, which means that some devices
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have a restricted number of channels that can be used.
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To allow flexibility for each CPU type and board, the
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DMA code can be given a DMA ordering structure which
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allows the order of channel search to be specified, as
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well as allowing the prohibition of certain claims.
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struct s3c24xx_dma_order has a list of channels, and
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each channel within has a slot for a list of DMA
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channel numbers. The slots are searched in order for
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the presence of a DMA channel number with DMA_CH_VALID
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or-ed in.
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If the order has the flag DMA_CH_NEVER set, then after
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checking the channel list, the system will return no
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found channel, thus denying the request.
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A board support file can call s3c24xx_dma_order_set()
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to register a complete ordering set. The routine will
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copy the data, so the original can be discarded with
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__initdata.
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Authour
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-------
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Ben Dooks,
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Copyright (c) 2007 Ben Dooks, Simtec Electronics
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Licensed under the GPL v2
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