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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: create sde-common device tree for holi target
Separate common SDE bindings in sde-common-dt file to avoid unwanted duplications between VM variants of the SDE files for holi target. Change-Id: I45cab5017c296ec8669892b5edd0a742b59011f4
This commit is contained in:
Krishna Manikandan
parent
332d0e66d6
commit
d087180fe4
2 changed files with 312 additions and 299 deletions
246
display/holi-sde-common.dtsi
Normal file
246
display/holi-sde-common.dtsi
Normal file
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@ -0,0 +1,246 @@
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#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@5e00000 {
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compatible = "qcom,sde-kms";
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reg = <0x05e00000 0x8f030>,
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<0x05eb0000 0x2008>,
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<0x05e8f000 0x030>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"sid_phys";
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clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>;
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clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000
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560000000>;
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/* interrupt config */
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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qcom,sde-ctl-off = <0x2000>;
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qcom,sde-ctl-size = <0x1dc>;
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qcom,sde-ctl-display-pref = "primary";
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qcom,sde-mixer-off = <0x45000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-intf-off = <0x0 0x6b800>;
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qcom,sde-intf-size = <0x2c0>;
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qcom,sde-intf-type = "none", "dsi";
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qcom,sde-intf-tear-irq-off = <0 0x6e800>;
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qcom,sde-pp-off = <0x71000>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-dsc-off = <0x81000>;
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qcom,sde-dsc-size = <0x140>;
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qcom,sde-dither-off = <0x30e0>;
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qcom,sde-dither-version = <0x00010000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "dma";
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qcom,sde-sspp-off = <0x5000 0x25000>;
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qcom,sde-sspp-src-size = <0x1f8>;
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qcom,sde-sspp-xin-id = <0 1>;
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qcom,sde-sspp-excl-rect = <1 1>;
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qcom,sde-sspp-smart-dma-priority = <2 1>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <0>;
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qcom,sde-mixer-stage-base-layer;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;
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qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
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qcom,sde-qseed-scalar-version = <0x3000>;
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-sspp-linewidth = <2160>;
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qcom,sde-vig-sspp-linewidth = <4096>;
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qcom,sde-scaling-linewidth = <2560>;
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qcom,sde-mixer-linewidth = <2048>;
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qcom,sde-mixer-blendstages = <0x4>;
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qcom,sde-highest-bank-bit = <0x0 0x1>;
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qcom,sde-ubwc-version = <0x200>;
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qcom,sde-ubwc-swizzle = <0x6>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-ubwc-static = <0x1e>;
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qcom,sde-macrotile-mode = <0x0>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-dim-layer;
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qcom,sde-max-bw-low-kbps = <5200000>;
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qcom,sde-max-bw-high-kbps = <6200000>;
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qcom,sde-min-core-ib-kbps = <2500000>;
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qcom,sde-min-llcc-ib-kbps = <0>;
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qcom,sde-min-dram-ib-kbps = <1600000>;
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qcom,sde-dram-channels = <1>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x2008>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
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qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
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qcom,sde-qos-refresh-rates = <60 120>;
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qcom,sde-danger-lut = <0xffff 0xffff 0x0
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0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0
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0x0 0x3ffff 0x3ffff>;
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qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>,
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<0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>;
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qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
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qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
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qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
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qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
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qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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qcom,sde-secure-sid-mask = <0x821>;
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qcom,sde-num-mnoc-ports = <1>;
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qcom,sde-axi-bus-width = <32>;
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qcom,sde-reg-bus,vectors-KBps = <0 0>,
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<0 76800>,
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<0 150000>,
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<0 300000>;
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qcom,sde-sspp-vig-blocks {
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xa0>;
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x0 0x00030001>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone= <0x900 0x00010007>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-pcc = <0x1700 0x00040000>;
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qcom,sde-dspp-gc = <0x17c0 0x00010008>;
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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};
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mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 {
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compatible = "qcom,dsi-ctrl-hw-v2.4";
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label = "dsi-ctrl-0";
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cell-index = <0>;
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frame-threshold-time-us = <1000>;
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reg = <0x05e94000 0x400>,
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<0x05f08000 0x4>;
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <21800>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 {
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compatible = "qcom,dsi-phy-v3.0";
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label = "dsi-phy-0";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x05e94400 0x800>,
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<0x05e94a00 0x1e0>,
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<0x05f01004 0x8>,
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<0x05e94200 0x100>;
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reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
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pll-label = "dsi_pll_10nm";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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55 03
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55 00];
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qcom,platform-lane-config = [00 00 00 00
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00 00 00 00
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00 00 00 00
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00 00 00 00
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00 00 00 80];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage =
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<RPMH_REGULATOR_LEVEL_NOM>;
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qcom,supply-max-voltage =
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<RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,supply-off-min-voltage =
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<RPMH_REGULATOR_LEVEL_RETENTION>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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};
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@ -1,3 +1,4 @@
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#include "holi-sde-common.dtsi"
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#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
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&soc {
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@ -6,201 +7,20 @@
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label = "disp_rdump_region";
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};
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mdss_mdp: qcom,mdss_mdp@5e00000 {
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compatible = "qcom,sde-kms";
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reg = <0x05e00000 0x8f030>,
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<0x05eb0000 0x2008>,
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<0x05e8f000 0x030>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"sid_phys";
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x820 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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};
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clocks =
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
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"div_clk",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>;
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clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000
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560000000>;
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sde-vdd-supply = <&mdss_core_gdsc>;
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/* interrupt config */
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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qcom,sde-ctl-off = <0x2000>;
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qcom,sde-ctl-size = <0x1dc>;
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qcom,sde-ctl-display-pref = "primary";
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qcom,sde-mixer-off = <0x45000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-intf-off = <0x0 0x6b800>;
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qcom,sde-intf-size = <0x2c0>;
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qcom,sde-intf-type = "none", "dsi";
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qcom,sde-intf-tear-irq-off = <0 0x6e800>;
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qcom,sde-pp-off = <0x71000>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-dsc-off = <0x81000>;
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qcom,sde-dsc-size = <0x140>;
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qcom,sde-dither-off = <0x30e0>;
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qcom,sde-dither-version = <0x00010000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "dma";
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qcom,sde-sspp-off = <0x5000 0x25000>;
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qcom,sde-sspp-src-size = <0x1f8>;
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qcom,sde-sspp-xin-id = <0 1>;
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qcom,sde-sspp-excl-rect = <1 1>;
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qcom,sde-sspp-smart-dma-priority = <2 1>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <0>;
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qcom,sde-mixer-stage-base-layer;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;
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qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
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qcom,sde-qseed-scalar-version = <0x3000>;
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-sspp-linewidth = <2160>;
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qcom,sde-vig-sspp-linewidth = <4096>;
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qcom,sde-scaling-linewidth = <2560>;
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qcom,sde-mixer-linewidth = <2048>;
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qcom,sde-mixer-blendstages = <0x4>;
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qcom,sde-highest-bank-bit = <0x0 0x1>;
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qcom,sde-ubwc-version = <0x200>;
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qcom,sde-ubwc-swizzle = <0x6>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-ubwc-static = <0x1e>;
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qcom,sde-macrotile-mode = <0x0>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-dim-layer;
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qcom,sde-has-idle-pc;
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||||
qcom,sde-max-bw-low-kbps = <5200000>;
|
||||
qcom,sde-max-bw-high-kbps = <6200000>;
|
||||
qcom,sde-min-core-ib-kbps = <2500000>;
|
||||
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||
qcom,sde-min-dram-ib-kbps = <1600000>;
|
||||
qcom,sde-dram-channels = <1>;
|
||||
qcom,sde-num-nrt-paths = <0>;
|
||||
|
||||
qcom,sde-vbif-off = <0>;
|
||||
qcom,sde-vbif-size = <0x2008>;
|
||||
qcom,sde-vbif-id = <0>;
|
||||
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
|
||||
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-qos-refresh-rates = <60 120>;
|
||||
qcom,sde-danger-lut = <0xffff 0xffff 0x0
|
||||
0x0 0xffff 0xffff>, <0x3ffff 0x3ffff 0x0
|
||||
0x0 0x3ffff 0x3ffff>;
|
||||
|
||||
qcom,sde-safe-lut = <0xff00 0xff00 0xffff 0x0000 0xff00 0xff00>,
|
||||
<0xfe00 0xfe00 0xffff 0x0000 0xfe00 0xfe00>;
|
||||
|
||||
qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
|
||||
qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
|
||||
qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
|
||||
qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
|
||||
qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
|
||||
|
||||
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
||||
|
||||
qcom,sde-qos-cpu-mask = <0x3>;
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
|
||||
qcom,sde-secure-sid-mask = <0x821>;
|
||||
qcom,sde-num-mnoc-ports = <1>;
|
||||
qcom,sde-axi-bus-width = <32>;
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>,
|
||||
<&bimc MASTER_AMPSS_M0
|
||||
&config_noc SLAVE_DISPLAY_CFG>;
|
||||
interconnect-names = "qcom,sde-data-bus0",
|
||||
"qcom,sde-reg-bus";
|
||||
qcom,sde-reg-bus,vectors-KBps = <0 0>,
|
||||
<0 76800>,
|
||||
<0 150000>,
|
||||
<0 300000>;
|
||||
|
||||
qcom,sde-sspp-vig-blocks {
|
||||
qcom,sde-vig-csc-off = <0x1a00>;
|
||||
qcom,sde-vig-qseed-off = <0xa00>;
|
||||
qcom,sde-vig-qseed-size = <0xa0>;
|
||||
};
|
||||
|
||||
qcom,sde-dspp-blocks {
|
||||
qcom,sde-dspp-igc = <0x0 0x00030001>;
|
||||
qcom,sde-dspp-hsic = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
|
||||
qcom,sde-dspp-hist = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
|
||||
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
|
||||
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
|
||||
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
|
||||
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||
};
|
||||
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "sde-vdd";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||
compatible = "qcom,smmu_sde_sec";
|
||||
iommus = <&apps_smmu 0x821 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xa>;
|
||||
};
|
||||
|
||||
mdss_rotator: qcom,mdss_rotator {
|
||||
|
|
@ -267,114 +87,61 @@
|
|||
qcom,iommu-vmid = <0xa>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.4";
|
||||
label = "dsi-ctrl-0";
|
||||
cell-index = <0>;
|
||||
frame-threshold-time-us = <1000>;
|
||||
reg = <0x05e94000 0x400>,
|
||||
<0x05f08000 0x4>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <4 0>;
|
||||
vdda-1p2-supply = <&L22A>;
|
||||
refgen-supply = <&refgen>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <21800>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "refgen";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 {
|
||||
compatible = "qcom,dsi-phy-v3.0";
|
||||
label = "dsi-phy-0";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0x05e94400 0x800>,
|
||||
<0x05e94a00 0x1e0>,
|
||||
<0x05f01004 0x8>,
|
||||
<0x05e94200 0x100>;
|
||||
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_10nm";
|
||||
vdda-0p9-supply = <&S5A_LEVEL>;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-lane-config = [00 00 00 00
|
||||
00 00 00 00
|
||||
00 00 00 00
|
||||
00 00 00 00
|
||||
00 00 00 80];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_NOM>;
|
||||
qcom,supply-max-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
qcom,supply-off-min-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x820 0x2>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-earlymap; /* for cont-splash */
|
||||
};
|
||||
|
||||
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||
compatible = "qcom,smmu_sde_sec";
|
||||
iommus = <&apps_smmu 0x821 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xa>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
clocks =
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>;
|
||||
clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
|
||||
"div_clk", "iface_clk", "core_clk",
|
||||
"vsync_clk", "lut_clk", "rot_clk";
|
||||
sde-vdd-supply = <&mdss_core_gdsc>;
|
||||
/* data and reg bus scale settings */
|
||||
interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI>,
|
||||
<&bimc MASTER_AMPSS_M0
|
||||
&config_noc SLAVE_DISPLAY_CFG>;
|
||||
interconnect-names = "qcom,sde-data-bus0",
|
||||
"qcom,sde-reg-bus";
|
||||
qcom,sde-has-idle-pc;
|
||||
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "sde-vdd";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L22A>;
|
||||
refgen-supply = <&refgen>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
vdda-0p9-supply = <&S5A_LEVEL>;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue