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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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spmi: pmic_arb: add support for hw version 2
Qualcomm PMIC Arbiter version-2 changes from version-1 are: - Some different register offsets. - New channel register space, one per PMIC peripheral (ppid). All tx traffic uses these channels. - New observer register space. All rx trafic uses this space. - Different command format for spmi command registers. Reviewed-by: Sagar Dharia <[email protected]> Signed-off-by: Gilad Avidov <[email protected]> Tested-by: Ivan T. Ivanov <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Gilad Avidov
Greg Kroah-Hartman
parent
0b9641f572
commit
d0c6ae41d1
2 changed files with 265 additions and 60 deletions
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@ -1,4 +1,5 @@
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -25,22 +26,18 @@
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/* PMIC Arbiter configuration registers */
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#define PMIC_ARB_VERSION 0x0000
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#define PMIC_ARB_VERSION_V2_MIN 0x20010000
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#define PMIC_ARB_INT_EN 0x0004
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/* PMIC Arbiter channel registers */
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#define PMIC_ARB_CMD(N) (0x0800 + (0x80 * (N)))
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#define PMIC_ARB_CONFIG(N) (0x0804 + (0x80 * (N)))
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#define PMIC_ARB_STATUS(N) (0x0808 + (0x80 * (N)))
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#define PMIC_ARB_WDATA0(N) (0x0810 + (0x80 * (N)))
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#define PMIC_ARB_WDATA1(N) (0x0814 + (0x80 * (N)))
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#define PMIC_ARB_RDATA0(N) (0x0818 + (0x80 * (N)))
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#define PMIC_ARB_RDATA1(N) (0x081C + (0x80 * (N)))
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/* Interrupt Controller */
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#define SPMI_PIC_OWNER_ACC_STATUS(M, N) (0x0000 + ((32 * (M)) + (4 * (N))))
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#define SPMI_PIC_ACC_ENABLE(N) (0x0200 + (4 * (N)))
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#define SPMI_PIC_IRQ_STATUS(N) (0x0600 + (4 * (N)))
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#define SPMI_PIC_IRQ_CLEAR(N) (0x0A00 + (4 * (N)))
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/* PMIC Arbiter channel registers offsets */
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#define PMIC_ARB_CMD 0x00
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#define PMIC_ARB_CONFIG 0x04
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#define PMIC_ARB_STATUS 0x08
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#define PMIC_ARB_WDATA0 0x10
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#define PMIC_ARB_WDATA1 0x14
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#define PMIC_ARB_RDATA0 0x18
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#define PMIC_ARB_RDATA1 0x1C
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#define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N))
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/* Mapping Table */
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#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
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@ -52,6 +49,7 @@
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#define SPMI_MAPPING_TABLE_LEN 255
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#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
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#define PPID_TO_CHAN_TABLE_SZ BIT(12) /* PPID is 12bit chan is 1byte*/
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/* Ownership Table */
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#define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
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@ -88,6 +86,7 @@ enum pmic_arb_cmd_op_code {
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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS 256
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#define PMIC_ARB_MAX_CHNL 128
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#define PMIC_ARB_PERIPH_ID_VALID (1 << 15)
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#define PMIC_ARB_TIMEOUT_US 100
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#define PMIC_ARB_MAX_TRANS_BYTES (8)
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@ -98,14 +97,17 @@ enum pmic_arb_cmd_op_code {
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/* interrupt enable bit */
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#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
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struct pmic_arb_ver_ops;
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/**
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* spmi_pmic_arb_dev - SPMI PMIC Arbiter object
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*
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* @base: address of the PMIC Arbiter core registers.
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* @rd_base: on v1 "core", on v2 "observer" register base off DT.
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* @wr_base: on v1 "core", on v2 "chnls" register base off DT.
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* @intr: address of the SPMI interrupt control registers.
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* @cnfg: address of the PMIC Arbiter configuration registers.
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* @lock: lock to synchronize accesses.
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* @channel: which channel to use for accesses.
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* @channel: execution environment channel to use for accesses.
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* @irq: PMIC ARB interrupt.
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* @ee: the current Execution Environment
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* @min_apid: minimum APID (used for bounding IRQ search)
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@ -113,10 +115,14 @@ enum pmic_arb_cmd_op_code {
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @domain: irq domain object for PMIC IRQ domain
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* @spmic: SPMI controller object
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* @apid_to_ppid: cached mapping from APID to PPID
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* @apid_to_ppid: in-memory copy of APID -> PPID mapping table.
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* @ver_ops: version dependent operations.
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* @ppid_to_chan in-memory copy of PPID -> channel (APID) mapping table.
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* v2 only.
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*/
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struct spmi_pmic_arb_dev {
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void __iomem *base;
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void __iomem *rd_base;
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void __iomem *wr_base;
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void __iomem *intr;
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void __iomem *cnfg;
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raw_spinlock_t lock;
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@ -129,17 +135,54 @@ struct spmi_pmic_arb_dev {
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struct irq_domain *domain;
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struct spmi_controller *spmic;
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u16 apid_to_ppid[256];
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const struct pmic_arb_ver_ops *ver_ops;
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u8 *ppid_to_chan;
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};
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/**
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* pmic_arb_ver: version dependent functionality.
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*
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* @non_data_cmd: on v1 issues an spmi non-data command.
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* on v2 no HW support, returns -EOPNOTSUPP.
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* @offset: on v1 offset of per-ee channel.
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* on v2 offset of per-ee and per-ppid channel.
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* @fmt_cmd: formats a GENI/SPMI command.
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* @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
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* on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn.
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* @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
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* on v2 offset of SPMI_PIC_ACC_ENABLEn.
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* @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
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* on v2 offset of SPMI_PIC_IRQ_STATUSn.
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* @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
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* on v2 offset of SPMI_PIC_IRQ_CLEARn.
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*/
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struct pmic_arb_ver_ops {
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/* spmi commands (read_cmd, write_cmd, cmd) functionality */
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u32 (*offset)(struct spmi_pmic_arb_dev *dev, u8 sid, u16 addr);
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u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
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int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
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/* Interrupts controller functionality (offset of PIC registers) */
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u32 (*owner_acc_status)(u8 m, u8 n);
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u32 (*acc_enable)(u8 n);
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u32 (*irq_status)(u8 n);
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u32 (*irq_clear)(u8 n);
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};
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static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
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{
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return readl_relaxed(dev->base + offset);
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return readl_relaxed(dev->rd_base + offset);
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}
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static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev *dev,
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u32 offset, u32 val)
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{
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writel_relaxed(val, dev->base + offset);
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writel_relaxed(val, dev->wr_base + offset);
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}
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static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev *dev,
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u32 offset, u32 val)
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{
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writel_relaxed(val, dev->rd_base + offset);
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}
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/**
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@ -168,15 +211,16 @@ pa_write_data(struct spmi_pmic_arb_dev *dev, const u8 *buf, u32 reg, u8 bc)
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pmic_arb_base_write(dev, reg, data);
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}
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static int pmic_arb_wait_for_done(struct spmi_controller *ctrl)
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static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
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void __iomem *base, u8 sid, u16 addr)
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{
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struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl);
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u32 status = 0;
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u32 timeout = PMIC_ARB_TIMEOUT_US;
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u32 offset = PMIC_ARB_STATUS(dev->channel);
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u32 offset = dev->ver_ops->offset(dev, sid, addr) + PMIC_ARB_STATUS;
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while (timeout--) {
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status = pmic_arb_base_read(dev, offset);
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status = readl_relaxed(base + offset);
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if (status & PMIC_ARB_STATUS_DONE) {
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if (status & PMIC_ARB_STATUS_DENIED) {
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@ -211,26 +255,43 @@ static int pmic_arb_wait_for_done(struct spmi_controller *ctrl)
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return -ETIMEDOUT;
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}
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/* Non-data command */
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static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
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static int
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pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
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{
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struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
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unsigned long flags;
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u32 cmd;
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int rc;
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u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, 0);
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cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0);
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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return rc;
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}
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static int
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pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
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{
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return -EOPNOTSUPP;
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}
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/* Non-data command */
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static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
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{
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struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
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dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
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/* Check for valid non-data command */
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if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
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return -EINVAL;
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cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pmic_arb_base_write(pmic_arb, PMIC_ARB_CMD(pmic_arb->channel), cmd);
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rc = pmic_arb_wait_for_done(ctrl);
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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return rc;
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return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
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}
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static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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@ -241,10 +302,11 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u8 bc = len - 1;
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u32 cmd;
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int rc;
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u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr);
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if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev,
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"pmic-arb supports 1..%d bytes per trans, but %d requested",
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"pmic-arb supports 1..%d bytes per trans, but:%zu requested",
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PMIC_ARB_MAX_TRANS_BYTES, len);
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return -EINVAL;
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}
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@ -259,20 +321,20 @@ static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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else
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return -EINVAL;
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cmd = (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
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cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pmic_arb_base_write(pmic_arb, PMIC_ARB_CMD(pmic_arb->channel), cmd);
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rc = pmic_arb_wait_for_done(ctrl);
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pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr);
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if (rc)
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goto done;
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pa_read_data(pmic_arb, buf, PMIC_ARB_RDATA0(pmic_arb->channel),
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pa_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
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min_t(u8, bc, 3));
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if (bc > 3)
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pa_read_data(pmic_arb, buf + 4,
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PMIC_ARB_RDATA1(pmic_arb->channel), bc - 4);
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offset + PMIC_ARB_RDATA1, bc - 4);
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done:
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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@ -287,10 +349,11 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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u8 bc = len - 1;
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u32 cmd;
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int rc;
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u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr);
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if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
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dev_err(&ctrl->dev,
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"pmic-arb supports 1..%d bytes per trans, but:%d requested",
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"pmic-arb supports 1..%d bytes per trans, but:%zu requested",
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PMIC_ARB_MAX_TRANS_BYTES, len);
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return -EINVAL;
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}
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@ -307,19 +370,19 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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else
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return -EINVAL;
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cmd = (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
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cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
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/* Write data to FIFOs */
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raw_spin_lock_irqsave(&pmic_arb->lock, flags);
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pa_write_data(pmic_arb, buf, PMIC_ARB_WDATA0(pmic_arb->channel)
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, min_t(u8, bc, 3));
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pa_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
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min_t(u8, bc, 3));
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if (bc > 3)
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pa_write_data(pmic_arb, buf + 4,
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PMIC_ARB_WDATA1(pmic_arb->channel), bc - 4);
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offset + PMIC_ARB_WDATA1, bc - 4);
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/* Start the transaction */
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pmic_arb_base_write(pmic_arb, PMIC_ARB_CMD(pmic_arb->channel), cmd);
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rc = pmic_arb_wait_for_done(ctrl);
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pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr);
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raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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return rc;
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@ -376,7 +439,7 @@ static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
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u32 status;
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int id;
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status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
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status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid));
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while (status) {
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id = ffs(status) - 1;
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status &= ~(1 << id);
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@ -402,7 +465,7 @@ static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
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for (i = first; i <= last; ++i) {
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status = readl_relaxed(intr +
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SPMI_PIC_OWNER_ACC_STATUS(pa->ee, i));
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pa->ver_ops->owner_acc_status(pa->ee, i));
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while (status) {
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id = ffs(status) - 1;
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status &= ~(1 << id);
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@ -422,7 +485,7 @@ static void qpnpint_irq_ack(struct irq_data *d)
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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writel_relaxed(1 << irq, pa->intr + SPMI_PIC_IRQ_CLEAR(apid));
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writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid));
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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data = 1 << irq;
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@ -439,10 +502,11 @@ static void qpnpint_irq_mask(struct irq_data *d)
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid));
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if (status & SPMI_PIC_ACC_ENABLE_BIT) {
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status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
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writel_relaxed(status, pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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writel_relaxed(status, pa->intr +
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pa->ver_ops->acc_enable(apid));
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}
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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@ -460,10 +524,10 @@ static void qpnpint_irq_unmask(struct irq_data *d)
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u8 data;
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raw_spin_lock_irqsave(&pa->lock, flags);
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status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid));
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if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) {
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writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT,
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pa->intr + SPMI_PIC_ACC_ENABLE(apid));
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pa->intr + pa->ver_ops->acc_enable(apid));
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}
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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|
|
@ -624,6 +688,91 @@ static int qpnpint_irq_domain_map(struct irq_domain *d,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* v1 offset per ee */
|
||||
static u32 pmic_arb_offset_v1(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr)
|
||||
{
|
||||
return 0x800 + 0x80 * pa->channel;
|
||||
}
|
||||
|
||||
/* v2 offset per ppid (chan) and per ee */
|
||||
static u32 pmic_arb_offset_v2(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr)
|
||||
{
|
||||
u16 ppid = (sid << 8) | (addr >> 8);
|
||||
u8 chan = pa->ppid_to_chan[ppid];
|
||||
|
||||
return 0x1000 * pa->ee + 0x8000 * chan;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
|
||||
{
|
||||
return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
|
||||
}
|
||||
|
||||
static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
|
||||
{
|
||||
return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
|
||||
}
|
||||
|
||||
static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n)
|
||||
{
|
||||
return 0x20 * m + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n)
|
||||
{
|
||||
return 0x100000 + 0x1000 * m + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_acc_enable_v1(u8 n)
|
||||
{
|
||||
return 0x200 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_acc_enable_v2(u8 n)
|
||||
{
|
||||
return 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_status_v1(u8 n)
|
||||
{
|
||||
return 0x600 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_status_v2(u8 n)
|
||||
{
|
||||
return 0x4 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_clear_v1(u8 n)
|
||||
{
|
||||
return 0xA00 + 0x4 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_clear_v2(u8 n)
|
||||
{
|
||||
return 0x8 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v1 = {
|
||||
.non_data_cmd = pmic_arb_non_data_cmd_v1,
|
||||
.offset = pmic_arb_offset_v1,
|
||||
.fmt_cmd = pmic_arb_fmt_cmd_v1,
|
||||
.owner_acc_status = pmic_arb_owner_acc_status_v1,
|
||||
.acc_enable = pmic_arb_acc_enable_v1,
|
||||
.irq_status = pmic_arb_irq_status_v1,
|
||||
.irq_clear = pmic_arb_irq_clear_v1,
|
||||
};
|
||||
|
||||
static const struct pmic_arb_ver_ops pmic_arb_v2 = {
|
||||
.non_data_cmd = pmic_arb_non_data_cmd_v2,
|
||||
.offset = pmic_arb_offset_v2,
|
||||
.fmt_cmd = pmic_arb_fmt_cmd_v2,
|
||||
.owner_acc_status = pmic_arb_owner_acc_status_v2,
|
||||
.acc_enable = pmic_arb_acc_enable_v2,
|
||||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
||||
.map = qpnpint_irq_domain_map,
|
||||
.xlate = qpnpint_irq_domain_dt_translate,
|
||||
|
|
@ -634,8 +783,10 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
struct spmi_pmic_arb_dev *pa;
|
||||
struct spmi_controller *ctrl;
|
||||
struct resource *res;
|
||||
u32 channel, ee;
|
||||
void __iomem *core;
|
||||
u32 channel, ee, hw_ver;
|
||||
int err, i;
|
||||
bool is_v1;
|
||||
|
||||
ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
|
||||
if (!ctrl)
|
||||
|
|
@ -645,12 +796,65 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
pa->spmic = ctrl;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
|
||||
pa->base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->base)) {
|
||||
err = PTR_ERR(pa->base);
|
||||
core = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(core)) {
|
||||
err = PTR_ERR(core);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
|
||||
is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
|
||||
|
||||
dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2),
|
||||
hw_ver);
|
||||
|
||||
if (is_v1) {
|
||||
pa->ver_ops = &pmic_arb_v1;
|
||||
pa->wr_base = core;
|
||||
pa->rd_base = core;
|
||||
} else {
|
||||
u8 chan;
|
||||
u16 ppid;
|
||||
u32 regval;
|
||||
|
||||
pa->ver_ops = &pmic_arb_v2;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"obsrvr");
|
||||
pa->rd_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->rd_base)) {
|
||||
err = PTR_ERR(pa->rd_base);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"chnls");
|
||||
pa->wr_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->wr_base)) {
|
||||
err = PTR_ERR(pa->wr_base);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
pa->ppid_to_chan = devm_kzalloc(&ctrl->dev,
|
||||
PPID_TO_CHAN_TABLE_SZ, GFP_KERNEL);
|
||||
if (!pa->ppid_to_chan) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
/*
|
||||
* PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
|
||||
* ppid_to_chan is an in-memory invert of that table.
|
||||
*/
|
||||
for (chan = 0; chan < PMIC_ARB_MAX_CHNL; ++chan) {
|
||||
regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan));
|
||||
if (!regval)
|
||||
continue;
|
||||
|
||||
ppid = (regval >> 8) & 0xFFF;
|
||||
pa->ppid_to_chan[ppid] = chan;
|
||||
}
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
|
||||
pa->intr = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->intr)) {
|
||||
|
|
@ -731,9 +935,6 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
if (err)
|
||||
goto err_domain_remove;
|
||||
|
||||
dev_dbg(&ctrl->dev, "PMIC Arb Version 0x%x\n",
|
||||
pmic_arb_base_read(pa, PMIC_ARB_VERSION));
|
||||
|
||||
return 0;
|
||||
|
||||
err_domain_remove:
|
||||
|
|
|
|||
Loading…
Reference in a new issue