From 0d0c74a974dcc43506b080278189755233c07c97 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 26 Aug 2020 16:40:38 +0530 Subject: [PATCH] ARM: dts: msm: Setting source ref_clk_src set to CXO source Setting source ref_clk_src set to CXO source. Change-Id: I43562882b9bb7636d4554ed3db7e97be647d301f --- qcom/shima-pcie.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fb61f3ce64f8..4a05eff1809e 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -62,6 +62,7 @@ interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, @@ -73,7 +74,7 @@ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie_0_pipe_clk>; - clock-names = "pcie_0_pipe_clk", + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",