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ARM: dts: r8a7794: Add L2 cache-controller node

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Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
This commit is contained in:
Geert Uytterhoeven 2015-06-02 14:34:35 +02:00 • committed by Simon Horman
commit d12a384a1b
1 changed files with 8 additions and 0 deletions
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8
arch/arm/boot/dts/r8a7794.dtsi
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@ -40,6 +40,7 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
next-level-cache = <&L2_CA7>;
};
cpu1: cpu@1 {
@ -47,9 +48,16 @@
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
next-level-cache = <&L2_CA7>;
};
};
L2_CA7: cache-controller@1 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;