From d13ff6d50d443bad7d2629fd87d1f1d5f8f9528a Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Wed, 19 May 2021 14:31:06 +0530 Subject: [PATCH] ARM: dts: msm: Add GPU support for monaco IoT Add devicetree node for A702 GPU and its properties. Change-Id: If1d446493e5dc6a1bcda553e023427ba7593d3d6 --- qcom/monaco-gpu.dtsi | 196 +++++++++++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 1 + 2 files changed, 197 insertions(+) create mode 100644 qcom/monaco-gpu.dtsi diff --git a/qcom/monaco-gpu.dtsi b/qcom/monaco-gpu.dtsi new file mode 100644 index 000000000000..7f42a35dae74 --- /dev/null +++ b/qcom/monaco-gpu.dtsi @@ -0,0 +1,196 @@ +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a702_zap"; + memory-region = <&pil_gpu_mem>; + }; + + msm_gpu: qcom,kgsl-3d0@5900000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0"; + status = "ok"; + + reg = <0x5900000 0x90000>, + <0x5961000 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc"; + + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + qcom,chipid = <0x07000201>; + + qcom,initial-pwrlevel = <4>; + qcom,idle-timeout = <80>; + qcom,gpu-bimc-interface-clk-freq = <768000000>; + + qcom,ubwc-mode = <2>; + qcom,min-access-length = <64>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0xe1c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&rpmcc RPM_SMD_BIMC_GPU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "iface_clk", "mem_iface_clk", "gmu_clk", + "smmu_vote", "bimc_gpu_clk"; + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <3>; + + interconnect-names = "gpu_icc_path"; + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* index=1 */ + , /* index=2 */ + , /* index=3 */ + , /* index=4 */ + , /* index=5 */ + , /* index=6 */ + , /* index=7 */ + , /* index=8 */ + , /* index=9 */ + , /* index=10 */ + , /* index=11 */ + ; /* index=12 */ + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1010000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <12>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <11>; + qcom,bus-min-ddr7 = <11>; + qcom,bus-max-ddr7 = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <9>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <470000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <5>; + qcom,bus-max-ddr7 = <8>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <310000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <3>; + qcom,bus-max-ddr7 = <4>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x59a0000 0x10000>; + + vddcx-supply = <&gpu_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0 1>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2 0>; + qcom,iommu-dma = "disabled"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 52493d28cfda..1ac73a2e798e 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1377,6 +1377,7 @@ #include "monaco-usb.dtsi" #include "monaco-thermal.dtsi" #include "monaco-vidc.dtsi" +#include "monaco-gpu.dtsi" &qupv3_se6_2uart { status = "ok";