A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 16:46:15 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "ARM: dts: msm: Update GPUCC clock node and GDSC for YUPIK"

Browse source
This commit is contained in:
qctecmdr 2020-11-24 12:44:42 -08:00 • committed by Gerrit - the friendly Code Review server
commit d1bcd59ada
4 changed files with 54 additions and 33 deletions
Download patch file Download diff file Expand all files Collapse all files

19
qcom/shima-gdsc.dtsi
View file

@ -6,6 +6,7 @@
regulator-name = "gcc_pcie_0_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
qcom,retain-regs;
status = "disabled";
};
@ -15,6 +16,7 @@
regulator-name = "gcc_pcie_1_gdsc";
qcom,gds-timeout = <500>;
qcom,no-status-check-on-disable;
qcom,retain-regs;
status = "disabled";
};
@ -22,6 +24,7 @@
compatible = "qcom,gdsc";
reg = <0x177004 0x4>;
regulator-name = "gcc_ufs_phy_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -29,6 +32,7 @@
compatible = "qcom,gdsc";
reg = <0x10f004 0x4>;
regulator-name = "gcc_usb30_prim_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -36,6 +40,7 @@
compatible = "qcom,gdsc";
reg = <0x19e004 0x4>;
regulator-name = "gcc_usb30_sec_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -116,6 +121,7 @@
compatible = "qcom,gdsc";
reg = <0xad0c120 0x4>;
regulator-name = "cam_cc_titan_top_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -123,6 +129,7 @@
compatible = "qcom,gdsc";
reg = <0xad07004 0x4>;
regulator-name = "cam_cc_bps_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -130,6 +137,7 @@
compatible = "qcom,gdsc";
reg = <0xad0a004 0x4>;
regulator-name = "cam_cc_ife_0_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -137,6 +145,7 @@
compatible = "qcom,gdsc";
reg = <0xad0b004 0x4>;
regulator-name = "cam_cc_ife_1_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -144,6 +153,7 @@
compatible = "qcom,gdsc";
reg = <0xad0b070 0x4>;
regulator-name = "cam_cc_ife_2_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -151,6 +161,7 @@
compatible = "qcom,gdsc";
reg = <0xad08004 0x4>;
regulator-name = "cam_cc_ipe_0_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -161,6 +172,7 @@
regulator-name = "disp_cc_mdss_core_gdsc";
proxy-supply = <&disp_cc_mdss_core_gdsc>;
qcom,proxy-consumer-enable;
qcom,retain-regs;
status = "disabled";
};
@ -186,6 +198,7 @@
regulator-name = "gpu_cx_gdsc";
hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
qcom,no-status-check-on-disable;
qcom,retain-regs;
status = "disabled";
};
@ -196,6 +209,7 @@
sw-reset = <&gpu_gx_sw_reset>;
domain-addr = <&gpu_gx_domain_addr>;
qcom,reset-aon-logic;
qcom,retain-regs;
status = "disabled";
};
@ -204,6 +218,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0d18 0x4>;
regulator-name = "video_cc_mvs0_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -211,6 +226,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0bf8 0x4>;
regulator-name = "video_cc_mvs0c_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -218,6 +234,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0d98 0x4>;
regulator-name = "video_cc_mvs1_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -225,6 +242,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0c98 0x4>;
regulator-name = "video_cc_mvs1c_gdsc";
qcom,retain-regs;
status = "disabled";
};
@ -232,6 +250,7 @@
compatible = "qcom,gdsc";
reg = <0xaaf2004 0x4>;
regulator-name = "video_cc_mvsc_gdsc";
qcom,retain-regs;
status = "disabled";
};
};

17
qcom/shima.dtsi
View file

@ -3896,22 +3896,18 @@
};
&gcc_pcie_0_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_pcie_1_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_ufs_phy_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_usb30_prim_gdsc {
qcom,retain-regs;
status = "ok"
};
@ -3951,7 +3947,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3960,7 +3955,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3968,7 +3962,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3976,7 +3969,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3984,7 +3976,6 @@
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -3993,7 +3984,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4002,7 +3992,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4010,7 +3999,6 @@
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4018,7 +4006,6 @@
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};
@ -4028,7 +4015,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4036,7 +4022,6 @@
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4045,7 +4030,6 @@
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
@ -4053,7 +4037,6 @@
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};

11
qcom/yupik-rumi.dtsi
View file

@ -1,3 +1,5 @@
#include <dt-bindings/clock/qcom,gcc-yupik.h>
&soc {
timer {
clock-frequency = <5000000>;
@ -75,3 +77,12 @@
&qupv3_se5_2uart {
qcom,rumi_platform;
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>;
};
&gpucc {
clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
};

40
qcom/yupik.dtsi
View file

@ -600,8 +600,12 @@
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
compatible = "qcom,yupik-gcc", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -621,8 +625,15 @@
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
compatible = "qcom,yupik-gpucc", "syscon";
reg = <0x3d90000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -1310,56 +1321,46 @@
#include "ipcc-test-yupik.dtsi"
&gcc_pcie_0_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_pcie_1_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_ufs_phy_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&gcc_usb30_prim_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&gcc_usb30_sec_gdsc {
compatible = "regulator-fixed";
qcom,support-hw-trigger;
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
compatible = "regulator-fixed";
status = "ok"
};
@ -1404,12 +1405,19 @@
};
&gpu_cx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&gpu_gx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};