From 9ec8ceb91d722127ad14a544df0aa6a74cbf76c4 Mon Sep 17 00:00:00 2001
From: Amine Najahi <anajahi@qti.qualcomm.com>
Date: Thu, 29 Oct 2020 12:01:46 -0400
Subject: [PATCH] ARM: dts: msm: add support for secondary display in TVM

Add missing DSI clock nodes and dsi connector for
secondary display in TVM.

Change-Id: I34dab33fc478bcefff67f282cac35694013202ad
---
 display/trustedvm-lahaina-sde-display.dtsi | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/display/trustedvm-lahaina-sde-display.dtsi b/display/trustedvm-lahaina-sde-display.dtsi
index 036205f97d18..f3799d5bb242 100644
--- a/display/trustedvm-lahaina-sde-display.dtsi
+++ b/display/trustedvm-lahaina-sde-display.dtsi
@@ -28,6 +28,23 @@
 	qcom,panel-te-source = <0>;
 };
 
-&mdss_mdp {
-	connectors = <&sde_dsi>;
+&sde_dsi1 {
+	clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>,
+			 <&clock_cpucc PCLK_MUX_0_CLK>,
+			 <&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>,
+			 <&clock_cpucc CPHY_PCLK_SRC_0_CLK>,
+			 <&clock_cpucc BYTECLK_SRC_0_CLK>,
+			 <&clock_cpucc BYTECLK_MUX_1_CLK>,
+			 <&clock_cpucc PCLK_MUX_1_CLK>,
+			 <&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>,
+			 <&clock_cpucc CPHY_PCLK_SRC_1_CLK>;
+	clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+			"cphy_byte_clk0", "cphy_pixel_clk0",
+			"mux_byte_clk1", "mux_pixel_clk1",
+			"cphy_byte_clk1", "cphy_pixel_clk1";
+	qcom,panel-te-source = <1>;
+};
+
+&mdss_mdp {
+	connectors = <&sde_dsi &sde_dsi1>;
 };