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clk: qcom: Remove measure support for unregistered clocks in Lahaina

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Remove debug measure support for clocks that are not registered with
the clock framework.

Change-Id: I69461a35ad219aec8d0cdd54666234ad01fbc1df
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
This commit is contained in:
Jagadeesh Kona 2020-12-29 16:00:38 +05:30
commit d1f568dc11
1 changed files with 0 additions and 18 deletions
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18
drivers/clk/qcom/debugcc-lahaina.c
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@ -88,7 +88,6 @@ static const char *const cam_cc_debug_mux_parent_names[] = {
"cam_cc_csiphy3_clk",
"cam_cc_csiphy4_clk",
"cam_cc_csiphy5_clk",
"cam_cc_gdsc_clk",
"cam_cc_icp_ahb_clk",
"cam_cc_icp_clk",
"cam_cc_ife_0_ahb_clk",
@ -163,7 +162,6 @@ static int cam_cc_debug_mux_sels[] = {
0xF, /* cam_cc_csiphy3_clk */
0x11, /* cam_cc_csiphy4_clk */
0x13, /* cam_cc_csiphy5_clk */
0x41, /* cam_cc_gdsc_clk */
0x36, /* cam_cc_icp_ahb_clk */
0x35, /* cam_cc_icp_clk */
0x26, /* cam_cc_ife_0_ahb_clk */
@ -266,7 +264,6 @@ static const char *const disp_cc_debug_mux_parent_names[] = {
"disp_cc_mdss_rscc_vsync_clk",
"disp_cc_mdss_vsync_clk",
"disp_cc_sleep_clk",
"disp_cc_xo_clk",
};
static int disp_cc_debug_mux_sels[] = {
@ -300,7 +297,6 @@ static int disp_cc_debug_mux_sels[] = {
0x2C, /* disp_cc_mdss_rscc_vsync_clk */
0x14, /* disp_cc_mdss_vsync_clk */
0x36, /* disp_cc_sleep_clk */
0x35, /* disp_cc_xo_clk */
};
static struct clk_debug_mux disp_cc_debug_mux = {
@ -342,7 +338,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
"gcc_camera_xo_clk",
"gcc_cfg_noc_usb3_prim_axi_clk",
"gcc_cfg_noc_usb3_sec_axi_clk",
"gcc_cpuss_ahb_clk",
"gcc_ddrss_gpu_axi_clk",
"gcc_ddrss_pcie_sf_tbu_clk",
"gcc_disp_ahb_clk",
@ -396,7 +391,6 @@ static const char *const gcc_debug_mux_parent_names[] = {
"gcc_qupv3_wrap1_s2_clk",
"gcc_qupv3_wrap1_s3_clk",
"gcc_qupv3_wrap1_s4_clk",
"gcc_qupv3_wrap1_s5_clk",
"gcc_qupv3_wrap2_core_2x_clk",
"gcc_qupv3_wrap2_core_clk",
"gcc_qupv3_wrap2_s0_clk",
@ -407,15 +401,12 @@ static const char *const gcc_debug_mux_parent_names[] = {
"gcc_qupv3_wrap2_s5_clk",
"gcc_qupv3_wrap_0_m_ahb_clk",
"gcc_qupv3_wrap_0_s_ahb_clk",
"gcc_qupv3_wrap_1_m_ahb_clk",
"gcc_qupv3_wrap_1_s_ahb_clk",
"gcc_qupv3_wrap_2_m_ahb_clk",
"gcc_qupv3_wrap_2_s_ahb_clk",
"gcc_sdcc2_ahb_clk",
"gcc_sdcc2_apps_clk",
"gcc_sdcc4_ahb_clk",
"gcc_sdcc4_apps_clk",
"gcc_sys_noc_cpuss_ahb_clk",
"gcc_throttle_pcie_ahb_clk",
"gcc_ufs_card_ahb_clk",
"gcc_ufs_card_axi_clk",
@ -487,7 +478,6 @@ static int gcc_debug_mux_sels[] = {
0x4C, /* gcc_camera_xo_clk */
0x1F, /* gcc_cfg_noc_usb3_prim_axi_clk */
0x20, /* gcc_cfg_noc_usb3_sec_axi_clk */
0xE3, /* gcc_cpuss_ahb_clk */
0xC9, /* gcc_ddrss_gpu_axi_clk */
0xCA, /* gcc_ddrss_pcie_sf_tbu_clk */
0x4E, /* gcc_disp_ahb_clk */
@ -541,7 +531,6 @@ static int gcc_debug_mux_sels[] = {
0x98, /* gcc_qupv3_wrap1_s2_clk */
0x99, /* gcc_qupv3_wrap1_s3_clk */
0x9A, /* gcc_qupv3_wrap1_s4_clk */
0x9B, /* gcc_qupv3_wrap1_s5_clk */
0x16E, /* gcc_qupv3_wrap2_core_2x_clk */
0x16D, /* gcc_qupv3_wrap2_core_clk */
0x16F, /* gcc_qupv3_wrap2_s0_clk */
@ -552,15 +541,12 @@ static int gcc_debug_mux_sels[] = {
0x174, /* gcc_qupv3_wrap2_s5_clk */
0x86, /* gcc_qupv3_wrap_0_m_ahb_clk */
0x87, /* gcc_qupv3_wrap_0_s_ahb_clk */
0x92, /* gcc_qupv3_wrap_1_m_ahb_clk */
0x93, /* gcc_qupv3_wrap_1_s_ahb_clk */
0x16B, /* gcc_qupv3_wrap_2_m_ahb_clk */
0x16C, /* gcc_qupv3_wrap_2_s_ahb_clk */
0x83, /* gcc_sdcc2_ahb_clk */
0x82, /* gcc_sdcc2_apps_clk */
0x85, /* gcc_sdcc4_ahb_clk */
0x84, /* gcc_sdcc4_apps_clk */
0xA, /* gcc_sys_noc_cpuss_ahb_clk */
0x40, /* gcc_throttle_pcie_ahb_clk */
0x107, /* gcc_ufs_card_ahb_clk */
0x106, /* gcc_ufs_card_axi_clk */
@ -706,25 +692,21 @@ static struct clk_debug_mux gpu_cc_debug_mux = {
};
static const char *const video_cc_debug_mux_parent_names[] = {
"video_cc_ahb_clk",
"video_cc_mvs0_clk",
"video_cc_mvs0c_clk",
"video_cc_mvs1_clk",
"video_cc_mvs1_div2_clk",
"video_cc_mvs1c_clk",
"video_cc_sleep_clk",
"video_cc_xo_clk",
};
static int video_cc_debug_mux_sels[] = {
0x7, /* video_cc_ahb_clk */
0x3, /* video_cc_mvs0_clk */
0x1, /* video_cc_mvs0c_clk */
0x5, /* video_cc_mvs1_clk */
0x8, /* video_cc_mvs1_div2_clk */
0x9, /* video_cc_mvs1c_clk */
0xC, /* video_cc_sleep_clk */
0xB, /* video_cc_xo_clk */
};
static struct clk_debug_mux video_cc_debug_mux = {