From d1f61b15be407898543b609b0aa49a05fb29da1a Mon Sep 17 00:00:00 2001
From: Deepak Kumar <dkumar@qti.qualcomm.com>
Date: Mon, 1 Feb 2021 14:49:42 +0530
Subject: [PATCH] ARM: dts: msm: Add apb_pclk to GMU clock list for Shima

apb_pclk is required to access QDSS registers. GMU need to add vote
before access can be made.

Change-Id: I26852622c0c453f56fe6d238a478283a0879e410
---
 qcom/shima-gpu.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi
index 7f15e0a95637..69e3fbc592f8 100644
--- a/qcom/shima-gpu.dtsi
+++ b/qcom/shima-gpu.dtsi
@@ -576,10 +576,12 @@
 			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 			<&gpucc GPU_CC_AHB_CLK>,
 			<&gpucc GPU_CC_HUB_CX_INT_CLK>,
-			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+			<&aopcc QDSS_CLK>;
 
 		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
-			"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote";
+			"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote",
+			"apb_pclk";
 
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";