mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Vr41xx: Fix after GENERIC_HARDIRQS_NO__DO_IRQ change [MIPS] SMTC: Instant IPI replay.
This commit is contained in:
Linus Torvalds
commit
d227e87e6c
5 changed files with 130 additions and 86 deletions
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -125,30 +125,17 @@ static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
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return data;
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}
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static unsigned int startup_giuint_low_irq(unsigned int irq)
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static void ack_giuint_low(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq);
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giu_write(GIUINTSTATL, 1 << pin);
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giu_set(GIUINTENL, 1 << pin);
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return 0;
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giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void shutdown_giuint_low_irq(unsigned int irq)
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static void mask_giuint_low(unsigned int irq)
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{
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giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void enable_giuint_low_irq(unsigned int irq)
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{
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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#define disable_giuint_low_irq shutdown_giuint_low_irq
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static void ack_giuint_low_irq(unsigned int irq)
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static void mask_ack_giuint_low(unsigned int irq)
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{
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unsigned int pin;
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@ -157,46 +144,30 @@ static void ack_giuint_low_irq(unsigned int irq)
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giu_write(GIUINTSTATL, 1 << pin);
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}
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static void end_giuint_low_irq(unsigned int irq)
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static void unmask_giuint_low(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static struct hw_interrupt_type giuint_low_irq_type = {
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.typename = "GIUINTL",
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.startup = startup_giuint_low_irq,
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.shutdown = shutdown_giuint_low_irq,
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.enable = enable_giuint_low_irq,
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.disable = disable_giuint_low_irq,
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.ack = ack_giuint_low_irq,
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.end = end_giuint_low_irq,
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static struct irq_chip giuint_low_irq_chip = {
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.name = "GIUINTL",
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.ack = ack_giuint_low,
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.mask = mask_giuint_low,
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.mask_ack = mask_ack_giuint_low,
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.unmask = unmask_giuint_low,
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};
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static unsigned int startup_giuint_high_irq(unsigned int irq)
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static void ack_giuint_high(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
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giu_write(GIUINTSTATH, 1 << pin);
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giu_set(GIUINTENH, 1 << pin);
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return 0;
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giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void shutdown_giuint_high_irq(unsigned int irq)
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static void mask_giuint_high(unsigned int irq)
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{
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giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void enable_giuint_high_irq(unsigned int irq)
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{
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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#define disable_giuint_high_irq shutdown_giuint_high_irq
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static void ack_giuint_high_irq(unsigned int irq)
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static void mask_ack_giuint_high(unsigned int irq)
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{
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unsigned int pin;
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@ -205,20 +176,17 @@ static void ack_giuint_high_irq(unsigned int irq)
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giu_write(GIUINTSTATH, 1 << pin);
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}
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static void end_giuint_high_irq(unsigned int irq)
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static void unmask_giuint_high(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static struct hw_interrupt_type giuint_high_irq_type = {
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.typename = "GIUINTH",
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.startup = startup_giuint_high_irq,
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.shutdown = shutdown_giuint_high_irq,
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.enable = enable_giuint_high_irq,
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.disable = disable_giuint_high_irq,
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.ack = ack_giuint_high_irq,
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.end = end_giuint_high_irq,
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static struct irq_chip giuint_high_irq_chip = {
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.name = "GIUINTH",
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.ack = ack_giuint_high,
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.mask = mask_giuint_high,
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.mask_ack = mask_ack_giuint_high,
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.unmask = unmask_giuint_high,
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};
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static int giu_get_irq(unsigned int irq)
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@ -282,9 +250,15 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPL, mask);
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giu_clear(GIUINTHTSELL, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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@ -311,9 +285,15 @@ void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPH, mask);
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giu_clear(GIUINTHTSELH, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATH, mask);
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}
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@ -617,10 +597,11 @@ static const struct file_operations gpio_fops = {
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static int __devinit giu_probe(struct platform_device *dev)
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{
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unsigned long start, size, flags = 0;
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unsigned int nr_pins = 0;
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unsigned int nr_pins = 0, trigger, i, pin;
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struct resource *res1, *res2 = NULL;
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void *base;
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int retval, i;
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struct irq_chip *chip;
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int retval;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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@ -688,11 +669,20 @@ static int __devinit giu_probe(struct platform_device *dev)
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giu_write(GIUINTENL, 0);
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giu_write(GIUINTENH, 0);
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trigger = giu_read(GIUINTTYPH) << 16;
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trigger |= giu_read(GIUINTTYPL);
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for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
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if (i < GIU_IRQ(GIUINT_HIGH_OFFSET))
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irq_desc[i].chip = &giuint_low_irq_type;
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pin = GPIO_PIN_OF_IRQ(i);
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if (pin < GIUINT_HIGH_OFFSET)
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chip = &giuint_low_irq_chip;
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else
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irq_desc[i].chip = &giuint_high_irq_type;
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chip = &giuint_high_irq_chip;
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if (trigger & (1 << pin))
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set_irq_chip_and_handler(i, chip, handle_edge_irq);
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else
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set_irq_chip_and_handler(i, chip, handle_level_irq);
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}
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return cascade_irq(GIUINT_IRQ, giu_get_irq);
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