From 58486553d399d7f3f2192bbf07a5a431afe5d482 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Mon, 8 Feb 2021 23:03:44 +0530 Subject: [PATCH 1/2] ARM: dts: msm: disable masking MSI interrupts at EP side Disable masking MSI interrupts at EP side. Change-Id: I79965e7ad50ea21bf6503d8474e223f5094738ea --- qcom/shima-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index e5909870ea8e..679206758308 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -114,6 +114,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,msi_mask_disable; qcom,phy-manage-pll = <1>; qcom,phy-resetsm-cntrl2 = <0xa0>; From 34ca1cf8152b7ae344155ca31d38d107160fb350 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Mon, 8 Feb 2021 23:13:48 +0530 Subject: [PATCH 2/2] dt-bindings: arm: msm: Add entry to disable masking MSI interrupts at EP Disable masking MSI interrupts at EP side. Change-Id: Idd7af1bcb6839964bf385158a75596c0978af6da --- bindings/pci/pci-msm.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 27741ba20e1c..5998845151a4 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -400,6 +400,9 @@ interconnects: Value type: Definition: PCIe PHY initialization sequence +- qcom,msi_mask_disable: + Usage: optional + Definition: Disable masking MSI interrupts at EP side ============== Root port node