diff --git a/drivers/firmware/qcom_scm-smc.c b/drivers/firmware/qcom_scm-smc.c
index 093500f3f89a..70f3b6f5330f 100644
--- a/drivers/firmware/qcom_scm-smc.c
+++ b/drivers/firmware/qcom_scm-smc.c
@@ -1326,6 +1326,26 @@ int __qcom_scm_smmu_prepare_atos_id(struct device *dev, u64 dev_id, int cb_num,
 	return ret;
 }
 
+int __qcom_mdf_assign_memory_to_subsys(struct device *dev, u64 start_addr,
+	u64 end_addr, phys_addr_t paddr, u64 size)
+{
+	int ret;
+	struct qcom_scm_desc desc = {
+		.svc = QCOM_SCM_SVC_MP,
+		.cmd = QCOM_SCM_MP_MPU_LOCK_NS_REGION,
+		.owner = ARM_SMCCC_OWNER_SIP
+	};
+
+	desc.args[0] = start_addr;
+	desc.args[1] = end_addr;
+	desc.args[2] = paddr;
+	desc.args[3] = size;
+	desc.arginfo = QCOM_SCM_ARGS(4);
+	ret = qcom_scm_call(dev, &desc);
+
+	return ret ? : desc.res[0];
+}
+
 bool __qcom_scm_dcvs_core_available(struct device *dev)
 {
 	return __qcom_scm_is_call_available(dev, QCOM_SCM_SVC_DCVS,
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 949f283a22dd..477e99c53adf 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -569,6 +569,18 @@ int qcom_scm_smmu_prepare_atos_id(u64 dev_id, int cb_num, int operation)
 }
 EXPORT_SYMBOL(qcom_scm_smmu_prepare_atos_id);
 
+/**
+ * qcom_mdf_assign_memory_to_subsys - SDE memory protect.
+ *
+ */
+int qcom_mdf_assign_memory_to_subsys(u64 start_addr, u64 end_addr,
+		phys_addr_t paddr, u64 size)
+{
+	return __qcom_mdf_assign_memory_to_subsys(__scm->dev,
+		start_addr, end_addr, paddr, size);
+}
+EXPORT_SYMBOL(qcom_mdf_assign_memory_to_subsys);
+
 /**
  * qcom_scm_dcvs_core_available() - check if core DCVS operations are available
  */
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index fb8fb0a6a883..b7c315352b88 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -83,6 +83,7 @@ extern void __qcom_scm_mmu_sync(struct device *dev, bool sync);
 #define QCOM_SCM_MEMP_SHM_BRIDGE_DELETE		0x1d
 #define QCOM_SCM_MEMP_SHM_BRDIGE_CREATE		0x1e
 #define QCOM_SCM_MP_SMMU_PREPARE_ATOS_ID	0x21
+#define QCOM_SCM_MP_MPU_LOCK_NS_REGION		0x25
 extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
 				      u32 spare);
 extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
@@ -120,6 +121,8 @@ extern int __qcom_scm_create_shm_bridge(struct device *dev,
 			u64 size_and_flags, u64 ns_vmids, u64 *handle);
 extern int __qcom_scm_smmu_prepare_atos_id(struct device *dev, u64 dev_id,
 						int cb_num, int operation);
+extern int __qcom_mdf_assign_memory_to_subsys(struct device *dev,
+		u64 start_addr, u64 end_addr, phys_addr_t paddr, u64 size);
 #define QCOM_SCM_IOMMU_TLBINVAL_FLAG    0x00000001
 #define QCOM_SCM_CP_APERTURE_REG	0x0
 
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index aafe1064d8ee..8581a1056c4e 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -78,6 +78,8 @@ extern bool qcom_scm_kgsl_set_smmu_aperture_available(void);
 extern int qcom_scm_kgsl_set_smmu_aperture(
 				unsigned int num_context_bank);
 extern int qcom_scm_smmu_prepare_atos_id(u64 dev_id, int cb_num, int operation);
+extern int qcom_mdf_assign_memory_to_subsys(u64 start_addr,
+				u64 end_addr, phys_addr_t paddr, u64 size);
 extern bool qcom_scm_dcvs_core_available(void);
 extern bool qcom_scm_dcvs_ca_available(void);
 extern int qcom_scm_dcvs_reset(void);
@@ -188,6 +190,9 @@ static inline int qcom_scm_kgsl_set_smmu_aperture(
 		unsigned int num_context_bank) { return -ENODEV; }
 static inline int qcom_scm_smmu_prepare_atos_id(u64 dev_id, int cb_num,
 		int operation) { return -ENODEV; }
+static inline int qcom_mdf_assign_memory_to_subsys(struct device *dev,
+		u64 start_addr, u64 end_addr, phys_addr_t paddr, u64 size)
+		{ return -ENODEV; }
 static inline bool qcom_scm_dcvs_core_available(void) { return false; }
 static inline bool qcom_scm_dcvs_ca_available(void) { return false; }
 static inline int qcom_scm_dcvs_init_v2(phys_addr_t addr, size_t size,