From c1846e805a6df07ff879f6f82722997e6f6e401d Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Tue, 24 Nov 2020 16:53:25 +0530 Subject: [PATCH] ARM: dts: msm: Update VideoCC node and Multimedia GDSC's for YUPIK Update VideoCC clock node and GDSC's of Camera, Display and Video clock controllers to real from dummy. Change-Id: I8a413d13a0b0406af09c8a38251dd4192bdf0676 --- qcom/yupik-rumi.dtsi | 4 ++++ qcom/yupik.dtsi | 45 +++++++++++++++++++++++++++++++++----------- 2 files changed, 38 insertions(+), 11 deletions(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 9ef144149b00..c4b5ffdcba88 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -174,3 +174,7 @@ clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>; }; + +&videocc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 2dae0b2503d4..768db173d15a 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -663,8 +663,13 @@ }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,yupik-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1827,41 +1832,55 @@ }; &cam_cc_titan_top_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; reg = <0xad0c194 0x4>; status = "ok"; }; &cam_cc_bps_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &cam_cc_ife_0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_1_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ife_2_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &cam_cc_ipe_0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &disp_cc_mdss_core_gdsc { - compatible = "regulator-fixed"; reg = <0xaf01004 0x4>; + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; @@ -1884,14 +1903,18 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; reg = <0xaaf3004 0x4>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; qcom,support-hw-trigger; status = "ok"; }; &video_cc_mvsc_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; };