From 9405d30b3d9ea564b225c7c2e35e7fc58a264981 Mon Sep 17 00:00:00 2001
From: Harshitha Sai Neelati <c_hsaine@qti.qualcomm.com>
Date: Thu, 25 Feb 2021 14:07:47 +0530
Subject: [PATCH] ARM: dts: msm: Add 128k and 265k pools for Lahaina

Add additional pools of size 128k and 256k to mempool.

Change-Id: Ibf563430d4b882dd0bece47b46af12ae00fccc0e
---
 qcom/lahaina-gpu.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi
index b95afe9c0a9a..925edea2b353 100644
--- a/qcom/lahaina-gpu.dtsi
+++ b/qcom/lahaina-gpu.dtsi
@@ -133,14 +133,12 @@
 				reg = <0>;
 				qcom,mempool-page-size = <4096>;
 				qcom,mempool-reserved = <2048>;
-				qcom,mempool-allocate;
 			};
 			/* 8K Page Pool configuration */
 			qcom,gpu-mempool@1 {
 				reg = <1>;
 				qcom,mempool-page-size = <8192>;
 				qcom,mempool-reserved = <1024>;
-				qcom,mempool-allocate;
 			};
 			/* 64K Page Pool configuration */
 			qcom,gpu-mempool@2 {
@@ -148,9 +146,21 @@
 				qcom,mempool-page-size = <65536>;
 				qcom,mempool-reserved = <256>;
 			};
-			/* 1M Page Pool configuration */
+			/* 128K Page Pool configuration */
 			qcom,gpu-mempool@3 {
 				reg = <3>;
+				qcom,mempool-page-size = <131072>;
+				qcom,mempool-reserved = <128>;
+			};
+			/* 256K Page Pool configuration */
+			qcom,gpu-mempool@4 {
+				reg = <4>;
+				qcom,mempool-page-size = <262144>;
+				qcom,mempool-reserved = <80>;
+			};
+			/* 1M Page Pool configuration */
+			qcom,gpu-mempool@5 {
+				reg = <5>;
 				qcom,mempool-page-size = <1048576>;
 				qcom,mempool-reserved = <32>;
 			};