mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
[ARM] S3C24XX: Additional include moves
Continue moving the include files into arch/arm Signed-off-by: Ben Dooks <[email protected]>
This commit is contained in:
Ben Dooks
parent
a2b7ba9ca4
commit
d5120ae72a
46 changed files with 47 additions and 47 deletions
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/* linux/include/asm-arm/plat-s3c/map.h
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*
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* Copyright 2003, 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C - Memory map definitions (virtual addresses)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_MAP_H
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#define __ASM_PLAT_MAP_H __FILE__
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/* Fit all our registers in at 0xF4000000 upwards, trying to use as
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* little of the VA space as possible so vmalloc and friends have a
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* better chance of getting memory.
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*
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* we try to ensure stuff like the IRQ registers are available for
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* an single MOVS instruction (ie, only 8 bits of set data)
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*/
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#define S3C_ADDR_BASE (0xF4000000)
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#ifndef __ASSEMBLY__
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#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
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#else
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#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
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#endif
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#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
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#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
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#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
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#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
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#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
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#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
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#endif /* __ASM_PLAT_MAP_H */
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@ -1,60 +0,0 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
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*
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* Copyright (c) 2004 Shannon Holland <holland@loser.net>
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*
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* This program is free software; yosu can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 ADC registers
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*/
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#ifndef __ASM_ARCH_REGS_ADC_H
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#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
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#define S3C2410_ADCREG(x) (x)
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#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
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#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
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#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
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#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
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#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
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/* ADCCON Register Bits */
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#define S3C2410_ADCCON_ECFLG (1<<15)
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#define S3C2410_ADCCON_PRSCEN (1<<14)
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#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
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#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
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#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
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#define S3C2410_ADCCON_MUXMASK (0x7<<3)
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#define S3C2410_ADCCON_STDBM (1<<2)
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#define S3C2410_ADCCON_READ_START (1<<1)
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#define S3C2410_ADCCON_ENABLE_START (1<<0)
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#define S3C2410_ADCCON_STARTMASK (0x3<<0)
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/* ADCTSC Register Bits */
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#define S3C2410_ADCTSC_YM_SEN (1<<7)
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#define S3C2410_ADCTSC_YP_SEN (1<<6)
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#define S3C2410_ADCTSC_XM_SEN (1<<5)
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#define S3C2410_ADCTSC_XP_SEN (1<<4)
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#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
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#define S3C2410_ADCTSC_AUTO_PST (1<<2)
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#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
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/* ADCDAT0 Bits */
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#define S3C2410_ADCDAT0_UPDOWN (1<<15)
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#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
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#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
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#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
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/* ADCDAT1 Bits */
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#define S3C2410_ADCDAT1_UPDOWN (1<<15)
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#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
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#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
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#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
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#endif /* __ASM_ARCH_REGS_ADC_H */
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@ -1,155 +0,0 @@
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/* linux/include/asm-arm/plat-s3c/uncompress.h
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*
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* Copyright 2003, 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C - uncompress code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_UNCOMPRESS_H
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#define __ASM_PLAT_UNCOMPRESS_H
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typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
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/* uart setup */
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static unsigned int fifo_mask;
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static unsigned int fifo_max;
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/* forward declerations */
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static void arch_detect_cpu(void);
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/* defines for UART registers */
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#include <plat/regs-serial.h>
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#include <asm/plat-s3c/regs-watchdog.h>
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/* working in physical space... */
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#undef S3C2410_WDOGREG
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#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
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/* how many bytes we allow into the FIFO at a time in FIFO mode */
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#define FIFO_MAX (14)
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#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
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static __inline__ void
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uart_wr(unsigned int reg, unsigned int val)
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{
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volatile unsigned int *ptr;
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ptr = (volatile unsigned int *)(reg + uart_base);
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*ptr = val;
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}
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static __inline__ unsigned int
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uart_rd(unsigned int reg)
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{
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volatile unsigned int *ptr;
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ptr = (volatile unsigned int *)(reg + uart_base);
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return *ptr;
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}
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/* we can deal with the case the UARTs are being run
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* in FIFO mode, so that we don't hold up our execution
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* waiting for tx to happen...
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*/
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static void putc(int ch)
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{
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if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
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int level;
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while (1) {
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level = uart_rd(S3C2410_UFSTAT);
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level &= fifo_mask;
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if (level < fifo_max)
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break;
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}
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} else {
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/* not using fifos */
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while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
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barrier();
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}
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/* write byte to transmission register */
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uart_wr(S3C2410_UTXH, ch);
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}
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static inline void flush(void)
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{
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}
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#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
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/* CONFIG_S3C_BOOT_WATCHDOG
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*
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* Simple boot-time watchdog setup, to reboot the system if there is
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* any problem with the boot process
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*/
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#ifdef CONFIG_S3C_BOOT_WATCHDOG
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#define WDOG_COUNT (0xff00)
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static inline void arch_decomp_wdog(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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}
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static void arch_decomp_wdog_start(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
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}
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#else
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#define arch_decomp_wdog_start()
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#define arch_decomp_wdog()
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#endif
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#ifdef CONFIG_S3C_BOOT_ERROR_RESET
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static void arch_decomp_error(const char *x)
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{
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putstr("\n\n");
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putstr(x);
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putstr("\n\n -- System resetting\n");
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__raw_writel(0x4000, S3C2410_WTDAT);
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__raw_writel(0x4000, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
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while(1);
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}
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#define arch_error arch_decomp_error
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#endif
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static void error(char *err);
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static void
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arch_decomp_setup(void)
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{
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/* we may need to setup the uart(s) here if we are not running
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* on an BAST... the BAST will have left the uarts configured
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* after calling linux.
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*/
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arch_detect_cpu();
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arch_decomp_wdog_start();
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}
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#endif /* __ASM_PLAT_UNCOMPRESS_H */
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/* linux/include/asm-arm/plat-s3c24xx/clock.h
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* linux/arch/arm/mach-s3c2410/clock.h
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* http://www.simtec.co.uk/products/SWLINUX/
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* Written by Ben Dooks, <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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struct clk {
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struct list_head list;
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struct module *owner;
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struct clk *parent;
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const char *name;
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int id;
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int usage;
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unsigned long rate;
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unsigned long ctrlbit;
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int (*enable)(struct clk *, int enable);
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int (*set_rate)(struct clk *c, unsigned long rate);
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unsigned long (*get_rate)(struct clk *c);
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unsigned long (*round_rate)(struct clk *c, unsigned long rate);
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int (*set_parent)(struct clk *c, struct clk *parent);
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};
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/* other clocks which may be registered by board support */
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extern struct clk s3c24xx_dclk0;
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extern struct clk s3c24xx_dclk1;
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extern struct clk s3c24xx_clkout0;
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extern struct clk s3c24xx_clkout1;
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extern struct clk s3c24xx_uclk;
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extern struct clk clk_usb_bus;
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/* core clock support */
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extern struct clk clk_f;
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extern struct clk clk_h;
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extern struct clk clk_p;
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extern struct clk clk_mpll;
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extern struct clk clk_upll;
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extern struct clk clk_xtal;
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/* exports for arch/arm/mach-s3c2410
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*
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* Please DO NOT use these outside of arch/arm/mach-s3c2410
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*/
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extern struct mutex clocks_mutex;
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extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
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extern int s3c24xx_register_clock(struct clk *clk);
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extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
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extern int s3c24xx_setup_clocks(unsigned long xtal,
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unsigned long fclk,
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unsigned long hclk,
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unsigned long pclk);
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/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Common code for SMDK2410 and SMDK2440 boards
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*
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* http://www.fluff.org/ben/smdk2440/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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extern void smdk_machine_init(void);
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/* linux/include/asm-arm/plat-s3c24xx/dma.h
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*
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* Copyright (C) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C24XX DMA support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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extern struct sysdev_class dma_sysclass;
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extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
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#define DMA_CH_VALID (1<<31)
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#define DMA_CH_NEVER (1<<30)
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struct s3c24xx_dma_addr {
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unsigned long from;
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unsigned long to;
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};
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/* struct s3c24xx_dma_map
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*
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* this holds the mapping information for the channel selected
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* to be connected to the specified device
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*/
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struct s3c24xx_dma_map {
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const char *name;
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struct s3c24xx_dma_addr hw_addr;
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unsigned long channels[S3C2410_DMA_CHANNELS];
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unsigned long channels_rx[S3C2410_DMA_CHANNELS];
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};
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struct s3c24xx_dma_selection {
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struct s3c24xx_dma_map *map;
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unsigned long map_size;
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unsigned long dcon_mask;
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void (*select)(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map);
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void (*direction)(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map,
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enum s3c2410_dmasrc dir);
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};
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extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
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/* struct s3c24xx_dma_order_ch
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*
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* channel map for one of the `enum dma_ch` dma channels. the list
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* entry contains a set of low-level channel numbers, orred with
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* DMA_CH_VALID, which are checked in the order in the array.
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*/
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struct s3c24xx_dma_order_ch {
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unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
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unsigned int flags; /* flags */
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};
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/* struct s3c24xx_dma_order
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*
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* information provided by either the core or the board to give the
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* dma system a hint on how to allocate channels
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*/
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struct s3c24xx_dma_order {
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struct s3c24xx_dma_order_ch channels[DMACH_MAX];
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};
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extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
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/* DMA init code, called from the cpu support code */
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extern int s3c2410_dma_init(void);
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extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
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unsigned int stride);
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/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Header file for s3c2412 cpu support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_CPU_S3C2412
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extern int s3c2412_init(void);
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extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
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extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
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extern void s3c2412_init_clocks(int xtal);
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extern int s3c2412_baseclk_add(void);
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#else
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#define s3c2412_init_clocks NULL
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#define s3c2412_init_uarts NULL
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#define s3c2412_map_io NULL
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||||
#define s3c2412_init NULL
|
||||
#endif
|
||||
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Reference in a new issue